International Business Machines Corporation

David Goren

Shlomo Shlafman

Rachel Gordin

Ullrich Richard Pfeiffer

Benny Sheinman

Leland Chang

Naigang Wang

Michael Zelikson

Scott Kevin Reynolds

Danny Elad

Brian Allan Floyd

Roi Carmon

Rajendran Krishnasamy

Phillip Francis Chapman

Raminderpal Singh

Youri V Tretiakov

Wayne H Woods

Amir Alon

Betty Livshitz

Alberto Valdes Garcia

Thomas E Morf

Israel A Wagner

Mihai A Sanduleanu

Donald J Papae

Israel Berger

Eliyahu Shamsaev

Sue Ellen Strang

Kurt Alan Tallman

Sherman Anatoly

Anatoly Sherman

John Katzenstein

A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

Slab inductor device providing efficient on-chip supply voltage conversion and regulation

A voltage conversion circuit such as a buck regulator circuit has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches. The voltage conversion circuit can also include means to reduce or cancel a detrimental effect of other wires on same chip, such as a power grid, that conduct a return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.

A multi-stage amplifier is provided that uses tunable transmission lines, as well as a calibration method for the multi-stage amplifiers. A multi-stage amplifier, comprises a plurality of tunable amplification stages, wherein each of the tunable amplification stages comprises a tunable resonator based on a transmission line having a tunable element. The tunable elements may vary a capacitance or an inductance to tune a frequency of an applied signal. A calibration method is provided for a multi-stage amplifier having a plurality of transmission lines, an input stage and an output stage. The multi-stage amplifier is calibrated by generating a signal to determine a frequency for a substantially maximum power; generating an error signal by comparing the frequency for the substantially maximum power with a desired frequency; varying a digital control code applied to each of the tunable transmission lines, input stage and output stage until the error signal satisfies predefined criteria.

Multi-stage amplifier using tunable transmission lines and frequency response calibration of same

A novel and useful fabricated variable transmission line that is tuned digitally is presented. Digital tuning of the variable transmission line enables the compensation of process variation in both the active and passive devices of the RF design. Along with several embodiments of the variable transmission line, the present invention also provides a method of compact modeling of the variable transmission line. The variable transmission line structure and compact modeling enables circuit level simulation using a parametric device that in one embodiment can be included as an integral part of a silicon foundry design kit.

Structure and compact modeling of variable transmission lines

A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology.

Layout determining for wide wire on-chip interconnect lines

A system and method for design and modeling of vertical interconnects for 3DI applications. A design and modeling methodology of vertical interconnects for 3DI applications includes models that represent the frequency dependent behavior of vertical interconnects by means of multi-segment RLC scalable filter networks. The networks allow for accuracy versus computation efficiency tradeoffs, while maintaining correct asymptotic behavior at both high and low frequency limits. In the framework of the model it is shown that a major effect is pronounced frequency dependent silicon substrate induced dispersion and loss effects, which is considered in through silicon via (TSV) parallel Y-element parameters, including capacitance and conductance.

Method and system for design and modeling of vertical interconnects for 3DI applications

Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications.

Integrated circuit transformer devices for on-chip millimeter-wave applications

A THz radiation detector comprising a plurality of antenna arms separated from a suspended platform by an isolating thermal air gap. The detector functions to concentrate THz radiation energy into the smaller suspended MEMS platform (e.g., membrane) upon which a thermal sensor element is located. The THz photon energy is converted into electrical energy by means of a pixilated antenna using capacitive coupling in order to couple this focused energy across the thermally isolated air gap and onto the suspended membrane on which the thermal sensor is located.

Monolithic passive THz detector with energy concentration on sub-pixel suspended MEMS thermal sensor

A tool for analog and mixed signal circuits includes a unit enabling a user to identify one or more critical interconnect lines in a chip architecture and one or more selectable, predefined topologies for said critical interconnect lines. Each topology includes one or more signal wires and a current return path. A majority of the electric field lines are contained within the boundary of the topology. The invention also includes a method for designing analog and mixed signal (AMS) integrated circuits (IC), including defining a chip architecture and a floor plan, identifying one or more critical interconnect lines and selecting pre-designed transmission line topologies for the critical interconnect lines.

Topologies and methodologies for AMS integrated circuit design

A method and system for design and modeling of transmission lines are provided. The method includes providing a set of models of core structures () of transmission line cells and expanding each of the models of core structures () to include different neighboring elements. The parameter characteristics of the expanded core structures (-) are compared to determine a model having a minimal sufficiently closed neighborhood environment. A closed neighborhood environment complies with design rules to ensure desired transmission line behavior in a real design environment. A model having a closed neighborhood environment can be used as a stand-alone model of the core structure describing the transmission line behavior in the actual design environment.

Method and system for design and modeling of transmission lines

A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.

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Nesher, Israel

David Goren