Texas Instruments Corporation

David Gonzalez, Jr

Aaron L Frank

Deepak Arabagatte Ramappa

John DeGenova

Srinavas Raghavan

Mark R Visokay

Jiong-Ping Lu

Honglin Guo

Linlin Chen

Clint Montgomery

Matthew W Losey

One embodiment relates to a method of fabricating an integrated circuit. In the method, p-type polysilicon is provided over a semiconductor body, where the p-type polysilicon has a first depth as measured from a top surface of the p-type polysilicon. An n-type dopant is implanted into the p-type polysilicon to form a counter-doped layer at the top-surface of the p-type polysilicon, where the counter-doped layer has a second depth that is less than the first depth. A catalyst metal is provided that associates with the counter-doped layer to form a catalytic surface. A metal is deposited over the catalytic surface. A thermal process is performed that reacts the metal with the p-type polysilicon in the presence of the catalytic surface to form a metal silicide. Other methods and devices are also disclosed.

Methods for full gate silicidation of metal gate structures

The present invention provides a system for removing organic contaminants () from a copper seed layer that has been deposited on a semiconductor substrate (). The present invention provides a housing () to enclose the semiconductor substrate within. An ultraviolet radiation source () is disposed within the housing. A treatment medium () is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.

System for ultraviolet atmospheric seed layer remediation

Apparatus and methods are disclosed for electroplating conductive films on semiconductor wafers, wherein field adjustment apparatus is located in a reservoir between a cathode and an anode to influence the electric field used in the plating process. Field adjustment apparatus is presented having one or more apertures, which may be selectively plugged to adjust the electrical fields during plating.

Methods and apparatus for improved current density and feature fill control in ECD reactors

A pre-ECD wet surface treatment. After forming the barrier material ( ) and seed layer ( ), the surface of the seed layer ( ) is treated with a water-based solution to remove surface contamination ( ) and improve wettability. The ECD copper film ( ) is then formed over the seed layer ( ).

Pre-ECD wet surface modification to improve wettability and reduced void defect

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Plano, TX, United States of America

David Gonzalez, Jr