Lsi Logic Corporation

Monterey Design Systems, Inc.

David Gluss

Michael D Rostoker

Douglas B Boyle

Jen-Hsun Huang

James S Koford

Lawrence Thomas Pileggi

Majid Sarrafzadeh

Salil Ravindra Raje

Sharad Malik

Christopher J Dunn

Gary K Yeap

Feroze P Taraporevala

Abhijeet Chakraborty

Dennis Yamamoto

Robert E Shortt

Lilly Shieh

Tong Gao

Emre Tuncer

Joseph T Rahmeh

Dinesh D Gaitonde

Eric McCaughrin

Sam Jung Kim

Archie Li

Yau-Tsun Steven Li

Satamurthy Pullela

Tom Harrington

Georgia Lazana

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Method for design optimization using logical and physical information

A technique is described for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.

Method and apparatus for interim in-situ testing of an electronic system

A method for testing the timing parameters of a system design is presented, especially suited for use in testing for timing violations between the pins of a semiconductor device. A description of the timing constraints of the various modules of a design is written in a common non-technical vernacular, and functions as an input file. A Timing Shell Generator converts the input file description into a simulator-environment-compatible output code-language file description. The output code-language file is operative to implement the timing constraints of the original input file during simulation such that any violations of the prescribed timing constraints are indicated to the tester who can then take appropriate action.

Method for testing design timing parameters using a timing shell

A technique for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.

Method and apparatus for interim, in-situ testing of an electronic

Growing community of inventors

Woodside, CA, United States of America

David Gluss