Freescale Semiconductor,inc.

Motorola Corporation

Sematech, Inc.

David Gilmer

Philip J Tobin

Olubunmi O Adetutu

Srikanth Balaji Samavedam

James Kenyon Schaeffer, Iii

Christopher C Hobbs

Hsing H Tseng

Mark Victor Raymond

Marius K Orlowski

Chun-Li Liu

William James Taylor, Jr

Rama I Hegde

Tushar Praful Merchant

Hsing-Huang Tseng

Dina H Triyoso

Chang Yong Kang

Paul Daniel Kirsch

Leonard John Borucki

Sangduk Park

Prasad V Alluri

Joel Barnett

Joe Mogab

Michael Rendon

Darrell Roan

Chanro Park

Iuval R Clejan

Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Capacitors, systems, and methods

A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (), such as HfO, is deposited on a semiconductor substrate. A sacrificial layer (), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area () of the substrate is exposed and gate dielectric over a second (nMOS, for example) area () of the substrate continues to be protected by the sacrificial layer. A first gate conductor material () is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

Method for fabricating dual-metal gate device

One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities

A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.

Semiconductor device having a metal carbide gate with an electropositive element and a method of making the same

A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.

Method of making metal gate transistors

A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same

Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same

A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.

Method for forming a layer using a purging gas in a semiconductor process

A semiconductor device ( ) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric ( ) is formed in a region of the device for higher voltage requirements, e.g. an I/O region ( ). A thinner second gate dielectric ( ) is formed in a region of the device for lower voltage requirements, e.g. a core device region ( ). First and second dielectrics are preferably silicon dioxide or oxynitride. A metal oxide ( ) is deposited over both dielectrics, followed by deposition of a gate electrode material ( ). By using a single metal oxide layer in forming the gate dielectric stack for each transistor, together with high quality silicon dioxide or oxynitride dielectric layers, problems associated with selective etching of the metal oxide may be avoided, as may problems associated with various interfaces between the metal oxide and damaged or treated surfaces.

Method for forming a dual gate oxide device using a metal oxide and resulting device

A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Transistor with layered high-K gate dielectric and method therefor

Techniques for forming gate dielectric layers ( ) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions ( ) are formed prior to formation of structures included in the gate structure ( ) of the semiconductor device, where the gate structures ( ) are preferably formed using low temperature operations that allow the amorphous silicon regions ( ) to remain in an amorphous state. Source/drain regions ( ) are formed in the amorphous silicon regions ( ), and then the substrate is annealed to recrystallize the amorphous regions.

Method of recrystallizing an amorphous region of a semiconductor

A hafnium-based dielectric layer, such as hafnium oxide (HfO ), is formed over a semiconductor substrate by flowing a hafnium-containing precursor of hafnium (Hf) and iodine (I) and an oxygen-containing precursor resulting in a high quality dielectric layer over the substrate. In one embodiment, the hafnium-containing precursor is Hafnium tetraiodide (HfI ). The two precursors may be applied simultaneously or alternately. The hafnium tetraiodide may be provided into a reaction chamber via sublimation or direct liquid injection.

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Austin, TX, United States of America

David Gilmer