Vlsi Technology, Inc.

David Gerard Spaniol

Peter Chambers

Joseph Murray

Ronald E Lange

Ken Jaramillo

The present invention comprises a multiple bus master PCI (peripheral component interconnect) bus system within an integrated circuit. The system of the present includes an integrated circuit fabricated onto a single semiconductor die. An internal PCI bus is built into the integrated circuit. The internal PCI bus is adapted to transmit and convey data signals. A plurality of PCI agents are built into the integrated circuit. Each of the plurality of PCI agents are designed to perform a respective function and each of the plurality of PCI agents are coupled to the internal PCI bus to transmit and receive data. The internal PCI bus and the plurality of PCI agents are built into the integrated circuit on the single semiconductor die to create a high performance device.

Multi-master PCI bus system within a single integrated circuit

The present invention comprises a priority arbitration system for interfacing a plurality of PCI agents coupled to a peripheral component interconnect (PCI) bus such that high priority PCI agents are satisfied without starving low priority PCI agents. The system of the present includes a PCI bus adapted to transmit data signals. At least one high priority PCI agent is coupled to the PCI bus. At least one low priority PCI agent is coupled to the PCI bus. An arbiter is coupled to the high priority PCI agent and the low priority PCI agent via the PCI bus. The arbiter grants ownership of the PCI bus to the high priority PCI agent prior to granting ownership to the low priority PCI agent. After being granted ownership, the high priority PCI agent becomes an interim low priority PCI agent. The low priority PCI agent is accorded a higher priority by the arbiter than the interim low priority PCI agent. The interim low priority PCI agent reverts to the high priority PCI agent subsequent to a grant to the low priority PCI agent. In this manner, the arbiter, by granting ownership of the PCI bus to the low priority PCI agent before granting ownership of the PCI bus to the interim low priority PCI agent, ensures the low priority PCI agent is not prevented from accessing the PCI bus by the high priority PCI agent.

Priority arbitration system providing low latency and guaranteed access

Within a single integrated circuit, a bus operates in accordance with a bus protocol. The bus protocol includes a first control signal which, when not implemented within a single integrated circuit, is implemented using a pull-up resistor and tri-state gates within functional blocks attached to the bus. A first functional block includes a first input line for receiving an input component of the first control signal, and includes first logic means for generating a first output component of the first control signal. A second functional block includes a second input line for receiving the input component of the first control signal, and includes second logic means for generating a second output component of the first control signal. A logic block includes first logic for generating the input component of the first control signal. The first logic utilizes the first output component and the second output component to generate the input component of the first control signal.

Logic implementation of control signals for on-silicon multi-master data

A PCI bus writes non-contiguous data in a maximum of two PCI bus write cycles. A Bridge is provided which can combine data within its write buffer such that non-contiguous data results. Some I/O devices on the PCI bus cannot handle non-contiguous data, so the Bridge detects non-contiguous data, and generates appropriate write cycles to the PCI bus to transfer this data in a contiguous fashion. The method described takes advantage of the multiple data phase capability of the PCI bus to transfer data at more than one address during one PCI bus write cycle, and optimizes these transfers to assure that all non-contiguous transfers can occur in only two PCI bus write cycles.

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Phoenix, AZ, United States of America

David Gerard Spaniol