Texas Instruments Corporation

David Gerald Farber

Tom Lii

Brian Keith Kirkpatrick

Robert Kraft

Ping Jiang

Douglas Ticknor Grider

Ting Yiu Tsui

Andrew McKerrow

Kenneth Joseph Newton

Craig Henry Huffman

William Wesley Dostalik

Steve Lytle

Fred Y Clark

Andrew L Vance

Brian E Goodllin

A method of forming an interconnect structure for an integrated circuit. A dielectric stack is formed on the substrate including an etch-stop layer, a low-k or ULK dielectric layer, and a hard mask layer. The low-k or ULK dielectric is etched using at least two etching processes wherein each etching process is followed by an etch repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. The photoresist may be removed using at least two ashing processes wherein each ashing process is followed by an ash repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma.

Low damage low-k dielectric etch

A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

Method of fabricating semiconductors

An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40&#xb0; C. and subsequently heating the integrated circuit to 80&#xb0; C. to 120&#xb0; C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.

Uniform, damage free nitride ETCH

Uniform, damage free nitride etch

An integrated circuit is formed to include a first polarity MOS transistor and a second, opposite, polarity MOS transistor. A hard mask of silicon-doped boron nitride (SiBN) with 1 atomic percent to 30 atomic percent silicon is formed over the first polarity MOS transistor and the second polarity MOS transistor. The hard mask is removed from source/drain regions of the first polarity MOS transistor and left in place over the second polarity MOS transistor. Semiconductor material is epitaxially grown at the source/drain regions of the first polarity MOS transistor while the hard mask is in place. Subsequently, the hard mask is removed from the second polarity MOS transistor.

Hard mask for source/drain epitaxy control

The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the metal contact opening by first etching the fourth layer of a multilayered hard mask structure to have a number of trenches that expose the third layer of the multilayered hard mask structure. Following this, the third, second, and first layers of the multilayered hard mask structure are selectively etched to expose uncovered regions on the top surface of an isolation layer that touches and lies over a source region and a drain region. The uncovered regions on the top surface of the isolation layer are then etched to form the metal contact openings.

Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined opening

A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.

Lateral uniformity in silicon recess etch

The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion () of a substrate () to a first etch process, the first etch process designed to etch at a first entry angle (&#x3b8;), and subjecting a second portion () of the substrate () to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (&#x3b8;).

Method for reducing line edge roughness for conductive features

Methods are provided for delineating different layers and interfaces for inspection of a semiconductor wafer, wherein a sectioned portion of a wafer is subjected to a reactive ion etch process before inspection using a scanning electron microscope.

Methods for inspection sample preparation

One aspect of the invention relates to a method of removing contaminants from a low-k film. The method involves forming a sacrificial layer over the contaminated film. The contaminants combine with the sacrificial layer and are removed by etching away the sacrificial layer. An effective material for the sacrificial layer is, for example, a silicon carbide. The method can be used to prevent the occurrence of pattern defects in chemically amplified photoresists formed over low-k films.

Method of passivating and/or removing contaminants on a low-k dielectric/copper surface

An embodiment of the invention is a metal layer of a back-end module where the height of the interconnects is greater than the height of the dielectric regions . Another embodiment of the invention is a method of fabricating a semiconductor wafer where the height of the interconnects is greater than the height of the dielectric regions

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Plano, TX, United States of America

David Gerald Farber