Marvell International Limited

Applied Micro Circuits Corporation

Qualcomm Incorporated

Marvellworld Trade Ltd.

David Geddes

Scott Furey

Michael J Moretti

Salil Suri

Thomas Wu

Tze Lei Poo

Gregory Burd

Heng Tang

Siu-Hung Fred Au

Xinhai Kang

Pantas Sutardja

Abhijeet Prakash Gole

Joseph Jun Cao

Hung W Goh

A method and apparatus uses a flexible buffering scheme in an XOR engine to generate checksums, allowing a user to recover data when a disk drive partly or completely fails. An XOR engine may include three or more arithmetic units and three or more local result buffers, which may be used to generate a combination of any of a 'P' checksum, a 'Q' checksum, and an unmodified copy of the user data, in a single read. The local result buffers and arithmetic units allow the use of multiple Galois field Multiply coefficients so that multiple distinct &#x201c;Q&#x201d; checksums may be generated with only one read of the user data.

Method and apparatus for flexible buffers in an XOR engine

A system including an interrupt generation module and a processing detection module. The interrupt generation module is configured to generate an interrupt when a first indicator is set to a first state, where the first indicator transitions to a second state when the interrupt is generated. The processing detection module is configured to detect when the interrupt is sent, set a second indicator to a third state to indicate when the interrupt is sent, and set the second indicator to a fourth state when the interrupt is processed.

Systems and methods for controlling flow of message signaled interrupts

The present disclosure describes apparatuses and techniques for tunneling transaction packets. In some aspects a packet is received from a peripheral device via a first data interface of a device. The packet includes an address for resource access and an identifier that identifies the peripheral device or a function thereof. Based on this identifier, it is determined whether the peripheral device is attempting to access an internal resource of the device or a resource of a host device connected to a second data interface of the device. If the peripheral device is attempting to access the resource of the host device, the packet is routed to the host device via the second data interface without modifying the address for resource access. By so doing, the peripheral device can exchange data with the host device without using address translation.

Tunneling transaction packets

A hardware implemented system and method of encryption key management may facilitate access to a connected device. In some embodiments, an Input/Output (I/O) controller coupled to a host system may comprise a cryptocontext memory that is only accessible via state machines running on the controller and a key unwrap engine to decrypt wrapped keys associated with commands received from the host system.

Hardware implemented key management system and method

Apparatus having corresponding methods and computer-readable media comprise: an interface to receive a first address in a first address space for one of a plurality of resources, wherein each resource is associated with a respective first aperture in the first address space, and a respective second aperture in a second address space; and a translation module to translate the first address to a second address in the second address space; wherein the translation module includes address translation logic to swap a first sequence of bits in the first address with a second sequence of the bits in the first address; wherein a number of the bits in the second sequence is determined according to a number of the resources; and wherein a number of the bits in the first sequence is determined according to a difference between a size of the first aperture and a size of the second aperture.

Address translation for SR-IOV virtual function apertures

A hardware architecture for encryption and decryption device can improve the encryption and decryption data rate by using parallel processing, and pipeline operation, and save footprint by sharing hardware components. The hardware architecture can also be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit to encrypt a second portion of the array of data blocks, and a data block combiner to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks.

Method and apparatus of high speed encryption and decryption

Systems, methods, and other embodiments associated with a unified hybrid input/output adapter are described. According to one embodiment, an apparatus includes an Input/Output (I/O) interconnect configured to connect with a host device and to provide communications with the host device. The apparatus also includes a network adapter connected to the I/O interconnect and configured to communicate with a network storage. The apparatus includes a host adapter connected to the I/O interconnect and configured to communicate with a first storage device and a second storage device. The first storage device has a higher latency than the second storage device. The apparatus further includes a storage logic configured to control the I/O interconnect to cause storage access requests from the host device to be cached in the second storage device via the host adapter.

Unified I/O adapter

An encryption device can include a tweaking value manager that is configured to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit that is configured to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit that is configured to encrypt a second portion of the array of data blocks into a second portion of encrypted data blocks based on corresponding tweaking values and the data encryption key, and a data block combiner that is configured to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks into an array of encrypted data blocks.

A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

Data frame processing

The disclosure provides a hardware architecture for encryption and decryption device. The hardware architecture can improve the encryption and decryption data rate by using parallel processing, and pipeline operation. Further, the hardware architecture can save footprint by sharing hardware components. Additionally, the hardware architecture can be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager that is configured to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit that is configured to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit that is configured to encrypt a second portion of the array of data blocks into a second portion of encrypted data blocks based on corresponding tweaking values and the data encryption key, and a data block combiner that is configured to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks into an array of encrypted data blocks.

Methods and apparatus for bridging network protocols are disclosed. A protocol bridge may be used to function as a target for a network processor while performing a target mode operation, while functioning as an initiator on behalf of the network processor while performing an initiator mode operation. In one embodiment, the protocol bridge determines the mode of operation based on information in a received frame's header. In another embodiment, the protocol bridge couples a Fiber Channel device to a storage processor on a packet-over-SONET network.

Method for bridging network protocols

Method and apparatus for implementing a data frame processing model

Methods and apparatus for bridging network protocols are disclosed. A protocol bridge may be used to function as a target for a network processor while performing a target mode operation, while functioning as an initiator on behalf of the network processor while performing an initiator mode operation. In one embodiment, the protocol bridge determines the mode of operation based on information in a received frame's header. In another embodiment, the protocol bridge couples a Fibre Channel device to a storage processor on a packet-over-SONET network.

Growing community of inventors

Fremont, CA, United States of America

David Geddes