Advanced Micro Devices Corporation

Nortel Networks Corporation

Other

David Gary Roberts

Mahesh Kumar

Robert Alan Williams

Jeffrey Stuart Hansell

Glen William Gibson

Din-I Tsai

Jiu An

Ramkrishna Vepa

Joseph A Brcich

Praveen Ghanashyam Shekokar

Bala Sankaranarayanan

Sam Rajarathinam

Kalaine Wong

Robert B O'Hara, Jr

Sanjay Dhawah

Henry Yeh

Methods and systems for identifying a local domain for a data packet received at an interface through a network are described herein. In one aspect of the invention, an exemplary method includes extracting the network protocol information from the data packet, determining a local domain ID based on multiple layers of network protocol information simultaneously, and assigning the local domain ID to the data packet. Other methods and systems are also described.

Methods and systems for processing network data packets

Methods and systems for processing a request of changing a first node having a first service connecting with a second node in a network environment are described herein. In one aspect of the invention, an exemplary method includes dynamically launching a second service at the first node, connecting the second service with the second node, directing requests for service to the second service, and terminating the first service. Other methods and systems are also described.

Methods and systems for changing a topology of a network

A method, apparatus, and system in which a network system includes a virtual graph composed of a plurality individual networks. A first individual network is associated with a first user. The first individual network includes a plurality of service modules modeled to be representing a first set of network elements. The second individual network is associated with a second user. The second individual network includes a plurality of service modules modeled to be representing a second set of network elements. The second set of network element differs in the type of network elements included in the second individual network and the topological order of the network elements in the second individual network than the first set of network elements.

Network system having a virtual-service-module

A reception indicator circuit is provided for use in an apparatus, wherein the apparatus enables a host system to receive information packets from a medium. The reception indicator circuit has a delay calculator, a byte count comparator and a signal asserter. The delay calculator selects and reads a reference delay value in one of N number of length-delay data storage elements. A reference length value contained in the one of N number of length-delay data storage elements corresponds to a length value of an information packet being received by the apparatus. The length value of the information packet is determined based on data in the information packet. The byte count comparator detects when the reference delay value number of bytes in the information packet have been received by the apparatus. The signal asserter asserts a reception indication signal when the byte count comparator detects that the reference delay value number of bytes in the information packet have been received by the apparatus. Alternatively, the reception indicator circuit may include a delay calculator that either calculates or selects an interrupt time. In such an alternate reception indicator circuit, the byte count comparator may be replaced by a delay comparator that determines when the interrupt time has elapsed. After the interrupt time has elapsed, the signal asserter asserts the reception indication signal. The apparatus may be a network peripheral, and the medium may be a communications network.

Information packet reception indicator for reducing the utilization of a host system processor unit

Method and system aspects control access through a synchronization primitive to a peripheral device in a processing system. A processing system in accordance with the present invention includes at least one central processing unit (CPU), and at least one peripheral device coupled to the at least one CPU, where the at least one peripheral device includes a synchronization primitive for controlling acquisition by at least one thread of execution from the at least one CPU. In a system aspect for controlling access, the system includes a circuit for sending a first signal from a component of the processing system to a synchronization primitive within the peripheral device to determine a state of the synchronization primitive, and acquiring control of the peripheral device when the synchronization primitive is in a released state. In a method for gaining control of a peripheral device in a processing system, the method includes sending a first signal from a component of the processing system to a semaphore register within the peripheral device to determine a bit pattern in the semaphore register, and acquiring control of the peripheral device when the semaphore register stores a first bit pattern.

System for accessing control to a peripheral device utilizing a

A data transfer method with peripheral precharge wherein a starting portion of an output data block targeted for a peripheral is transferred to an output buffer for the peripheral using programmed I/O or slave cycles and wherein a virtual address of the output data block is translated into a physical address while the peripheral begins transferring the starting portion from the output buffer and over an output path. A direct memory access operation by the peripheral transfers a remainder portion of the output data block into the output buffer.

Precharging an output peripheral for a direct memory access operation

Method and system aspects properly enable and disable a function in a peripheral device. In a system aspect, the system includes a processing system, and a control mechanism within the peripheral device and coupled to the processing system, the control mechanism controlling enabling and disabling of a function in the peripheral device. The control mechanism further includes a decoder coupled to the processing system, and a counter coupled to the decoder. In a method aspect, the method includes receiving first and second control signals at a control mechanism in the peripheral device from at least one component in the processing system, and maintaining a state of the peripheral device at a predetermined level according to a value of the control mechanism, wherein the first and second control signals alter the value of the control mechanism.

Method and system for enabling and disabling functions in a peripheral

A method and apparatus as provided that simplifies the software required for modifying the contents of a register. By adding one gate to the register, a single command can be written to the register to modify the states of multiple bits. The system reduces software overhead significantly when multiple registers must be modified.

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Fremont, CA, United States of America

David Gary Roberts