Altera Corporation

David Galloway

David Lewis

Valavan Manohararajah

Ryan Fung

Vaughn Betz

Jeffrey Christopher Chromczak

Tim Michael Vanderhoek

Tim Vanderhoek

A method of configuring a programmable integrated circuit device with a user logic design includes analyzing the user logic design to identify unidirectional logic paths within the user logic design and cyclic logic paths within the user logic design, assigning the cyclic logic paths to logic in a first portion of the programmable integrated circuit device that operates at a first data rate, assigning the unidirectional logic paths to logic in a second portion of the programmable integrated circuit device that operates at a second data rate lower than the first data rate, and pipelining the unidirectional data paths in the second portion of the programmable integrated circuit device to compensate for the lower second data rate. A programmable integrated circuit device adapted to carry out such method may have logic regions operating at different rates, including logic regions with programmably selectable data rates.

Heterogeneous programmable device and configuration software adapted therefor

An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.

Clocking for pipelined routing

A logic device includes a low-skew network that feeds a subset of elements on the logic device. The low-skew network includes a selector that can select from a plurality of signal sources which includes a first signal source and a second signal source, wherein the second signal source can reach at least one element outside of the subset.

Method and apparatus for composing and decomposing low-skew network using routing input

One embodiment relates to a circuit for pipelined direct-drive routing, the circuit including a routing multiplexer, a flip-flop, and a mode multiplexer. The output of the routing multiplexer is coupled to an input of the mode multiplexer and to the flip-flop. The output of the flip-flop is connected to another input of the mode multiplexer. The flip-flop may be directly connected to the routing multiplexer and the mode multiplexer, or, in an alternate embodiment, the flip-flop may be a member of a pipeline register pool. Another embodiment relates to a circuit for pipelined direct-drive routing which uses a pulse latch. Other embodiments relate to method for pipelined direct-drive routing which includes a degree of logical separation between logic elements and flip-flop elements. Another embodiment relates to a logic array block. Other embodiments, aspects, and features are also disclosed.

Pipelined direct drive routing fabric

A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining latency characteristics of the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, and retiming the configuration based on the second user input.

Specification of latency in programmable device configuration

A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify critical and near-critical cyclic logic paths within the user logic design, applying timing optimizations to the critical and near-critical cyclic logic paths, and retiming logic paths other than the critical and near-critical cyclic logic paths.

Programmable device configuration methods adapted to account for retiming

A method of configuring a programmable integrated circuit device with a user logic design includes accepting a first user input defining the user logic design, accepting a second user input defining multithreading characteristics of at least a portion the user logic design, determining a configuration of the programmable integrated circuit device having the user logic design, multithreading the at least a portion of the configuration based on the second user input, and retiming the multithreaded configuration.

Specification of multithreading in programmable device configuration

Method and apparatus for composing and decomposing low-skew networks

A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. The one or more equations are modified, or supplemented by adding one or more additional equations, by applying spreading forces to the cells that take into consideration classification types of the cells and restricted areas on the target device that do not support the classification types. Revised locations on the target device are determined for the cells by solving the modified one or more equations.

Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas

A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. Partitioning of cells of a first classification type is performed. One or more equations are modified in response to the partitioning. Revised locations on the target device are determined for the cells by solving the modified one or more equations. The partitioning procedure takes into consideration the classification types of cells as well as restricted areas on the target device.

Growing community of inventors

Toronto, Canada

David Galloway