Freescale Semiconductor,inc.

David G Wontor

Jie-Hua Zhao

Marc Alan Mangrum

George R Leal

Robert Joseph Wenzel

Edward R Prack

Brian D Sawyer

Scott K Pozder

Edward Outlaw Travis, Jr

Kevin John Hess

Brett P Wilkerson

Pak Leung

Peng Su

A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

Circuit device with at least partial packaging and method for forming

A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure () having a stiff structural component () positioned above and affixed to a conductive metal pad () formed in a last metal layer (). The die test structure () may also include a dedicated support structure () below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers (). After mounting the integrated circuit in a test device, a shear knife () is positioned for lateral movement to cause the shear knife to contact the stiff structural component (). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.

Mechanical integrity evaluation of low-k devices with bump shear

A circuit device () is placed within an opening of a conductive layer () which is then partially encapsulated with an encapsulant () so that the active surface of the circuit device () is coplanar with the conductive layer (). At least a portion of the conductive layer () may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device () may be placed on a conductive layer () such that an active surface of circuit device () is between conductive layer () and an opposite surface of circuit device (). The conductive layer () has at least one opening () to expose the active surface of circuit device (). The encapsulant () may be electrically conductive or electrically non-conductive.

A technique for alleviating the problems of defects caused by stress applied to bond pads () includes, prior to actually making an integrated circuit (), adding dummy metal lines () to interconnect layers () to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics () between the interconnect layers are of a low-k material. A critical area or force area () around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Integrated circuit having structural support for a flip-chip interconnect pad and method therefor

Circuit device with at least partial packaging, exposed active surface and a voltage reference plane

In one embodiment, circuit device () is placed within an opening of a conductive layer () which is then partially encapsulated with an encapsulant () so that the active surface of the circuit device () is coplanar with the conductive layer (). In this embodiment, at least a portion of the conductive layer () may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device () is placed on a conductive layer () such that an active surface of circuit device () is between conductive layer () and an opposite surface of circuit device (). In this embodiment, conductive layer () has at least one opening () to expose the active surface of circuit device (). The encapsulant () may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

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Austin, TX, United States of America

David G Wontor