Ciena Corporation

Nortel Networks Corporation

Avaya Inc.

Rockstar Consortium US LP

David G Stuart

James Tierney

Bradley D Venables

Sebastien Gareau

David Alan Brown

Stacy W Nichols

Daniel Claude Perras

David James Evans

John Andrew Earl

Hamid Assarpour

Andrew L Jarabek

Blake Toplis

Graham Thomsen

Markus Wandel

A network element includes a port; and a device with circuitry configured to encode data for communication to a second device via a plurality of physical channels, and utilize one of the plurality of physical channels as a dedicated timing channel with encoding thereon different from encoding on the other plurality of physical channels, and interface encoded data via the plurality of physical channels with the port for transmission and reception with a second device.

Tolerant PCS for accurate timestamping in disaggregated network elements and synchronization method

A system includes a first module with a first clock; a second module with a second clock; and an Ethernet network interconnecting the first module and the second module by N Ethernet paths, N&#x2265;2; wherein the first module is configured to provide timestamps encapsulated in replicated Ethernet packets to the second module over each of the N Ethernet paths for redundancy. The first module can be configured to obtain timestamps from a first clock with each timestamp having a sequence identifier, replicate each timestamp and its sequence identifier, and encapsulate each replicated timestamp and its sequence identifier in an Ethernet packet and transmit each Ethernet packet over one of the N Ethernet paths. The second module can be configured to receive Ethernet packets over the N Ethernet paths; and utilize a first Ethernet packet with a given sequence identifier for synchronization of the second clock with the first clock.

Hitless protection for packet based digitized clock distribution

A switch system includes interface circuitry configured to ingress and egress clients each including a stream of encoded blocks; and switch circuitry configured to switch the clients between the interface circuitry based on block boundaries of the stream of encoded blocks. The stream of encoded blocks can include 64 b/66 b encoding. Each block in the stream of encoded blocks can be switched intact.

Flexible Ethernet switching systems and methods

A switch system configured to switch Flexible Ethernet (FlexE) client services includes interface circuitry configured to ingress and egress FlexE clients; and switch circuitry communicatively coupled to the interface circuitry and configured to switch portions of the FlexE clients utilizing a cell switch and Optical Transport Network (OTN) over Packet (OPF) techniques. A method of switching Flexible Ethernet (FlexE) client services includes ingressing and egressing FlexE clients via interface circuitry; interfacing the FlexE clients with switch circuitry communicatively coupled to the interface circuitry; and switching portions of the FlexE clients with the switch circuitry utilizing a cell switch and Optical Transport Network (OTN) over Packet (OPF) techniques.

Flexible ethernet switching systems and methods

A Flexible Ethernet (FlexE) switch system configured to switch a FlexE client service includes interface circuitry configured to ingress and egress a plurality of FlexE clients; and switch circuitry configured to switch portions of the FlexE clients based on 64 b/66 b block boundaries between the interface circuitry. A node configured to switch a Flexible Ethernet (FlexE) client service in a network includes one or more line cards configured to ingress and egress a plurality of FlexE clients; and one or more switch fabrics configured to switch portions of the FlexE clients based on 64 b/66 b block boundaries between the one or more line cards.

The present disclosure provides a fabric ingress scheduler and method that distributes ingress packet traffic in a time division multiplex (TDM) system, both fabric interface aggregate and per connection, deterministically across fabric paths. Advantageously, the fabric ingress scheduler and method minimizes fabric latency and prevents fabric interface head-of-line blocking. The fabric ingress scheduler and method utilizes the fact that each connection flow has a known maximum rate which must be reserved through the fabric for prevention of data loss (essentially circuit switching using a packet fabric). In exemplary embodiments, the fabric interface supports per packet fabric path selection. Generally, the fabric ingress scheduler and method generally provides a deterministic scheduling of ingress packets to fabric paths.

Time division multiplex packet fabric ingress scheduler and method

A count of data segments is maintained. The count includes data segments in a queue and data segments in transit between a data source and the queue. A flow of data segments from the data source is controlled, based on a value of the count.

Managing flow control buffer

A method and system schedule data for dequeuing in a communication network. The communication network includes an eligible scheduling node, a scheduling context structure, and an existence of data structure. In response to determining that an eligible scheduling node does not contain at least one child identifier in the scheduling context structure, an eligible child is selected for dequeue from the existence of data structure. At least one eligible child from the existence of data structure is absorbed into the scheduling context structure. The at least one eligible child includes the child selected for dequeue. Absorbing a child includes removing the child identifier from the existence of data queue and adding the child identifier to the scheduling context structure.

Method and system for scheduler dominated merge of state changes

A method and system for scheduling data dequeuing in a data communication network having a plurality of data queues and a hierarchical scheduler with a plurality of scheduling nodes. A determination is made as to which scheduler nodes and which data queues are eligible for dequeuing scheduling based upon at least one predetermined data rate limitation and availability of data at an eligible descendant node. Data is scheduled for transmission from one of the plurality of data queues. Scheduling data for transmission includes selecting one or more child scheduler nodes which are descendents of the one data queue but to whom the eligible child is not known to be eligible.

Method and system for weight and rate scheduling

Improved systems and methods for processing data traveling in a network in an efficient manner are provided. In many network implementations input/output ports have one or a small number of bandwidths. These ports sometimes lead to higher bandwidth ports than the source or destination needs. A method and system are provided wherein some of the input and output ports are known to be underutilized. Only a relatively small number of output ports require a complicated merge scheduler that provides configurable data transmission 'fairness' between input ports. Accordingly, a method and system are provided wherein preprocessing of input data reduces the cost of the merge circuits required at the outputs.

Method and system for merging bandwidth in multiplexing flows

An apparatus and a method for sender-initiated credit recovery in a closed-loop credit based flow control system, includes assigning a number of credits to a sender unit in the credit based flow control system. The method also includes decrementing a credit count in the sender unit in response to the sender sending data to the receiver and incrementing the credit count in the sender unit in response to receiving returned credits from the receiver unit. The method also includes determining if a loss or gain in the number of credits in the credit based flow control system has occurred and adjusting the credit count based on the determined loss or gain.

Credit recovery in a credit based flow control system

Methods, systems, and networks for tracking multicast cell copies in a switch. The switch includes a plurality of output ports each having an associated output port register, and a port memory controller for receiving a bit map on the enqueue of a cell into the switch. The bit map includes a bit for each output port register. The port memory controller writes to each output port register the bit from the bit map for that port register. The value of a bit in an output port register indicates whether a copy of the enqueued cell is to be transmitted from the output port associated with that output port register.

Method and apparatus for port memory multicast common memory switches

In a multicast cell counting methodology, the use of banked memories for enqueuing and dequeuing a multicast cell count value spreads the memory accesses over multiple memories, yielding a reduction in the number of per memory accesses per cell cycle. A cell count value, representing the number of cell copies to be multicast, is written to a first memory on a cell enqueue, and retrieved from the first memory after a first cell dequeue. The cell count value is decremented to reflect the first cell dequeue, and transferred to a second memory.

Growing community of inventors

Almonte, Canada

David G Stuart