Mission Research Corporation

David G Mavis

Paul H Eaton

A temporally redundant latch for use in integrated circuit (IC) devices redundantly samples data output from logic or other circuitry at multiple time-shifted periods to provide multiple, independent data samples from which a correct data sample can be selected. The latch has three sampling circuits (e.g., D flip-flops or DICE latches) that sample the logic data output at three different and distinct sampling times. The latch also has a sample release circuit coupled to the sampling circuits to select and output a majority of the samples collected by the sampling circuits at a fourth time that again is different and distinct from the three sampling times. The latch affords both spatial parallelism due to the multiple parallel sampling circuits and temporal parallelism resulting from the clocking scheme involving multiple time-spaced clock signals. The temporally redundant latch is immune to upsets that might occur in the latch itself, as well as upsets that occur in the circuitry and upsets that might occur in any clocking and control signals on the IC device.

Temporally redundant latch for preventing single event disruptions in

A field programmable gate array has multiple logic units interconnected via level-0 routing structure to form tier 0 logic tiles. The level-0 routing structure has horizontal wiring and vertical wiring that is interconnected via a horizontal-to-vertical directional routing switch that transfers signals from the horizontal wiring to the vertical wiring. The tier 0 logic tiles are nested within and interconnected by a level-1 routing structure to form tier 1 logic tiles. The level-1 routing structure has horizontal wiring and vertical wiring that is interconnected via a vertical-to-horizontal directional routing switch that transfers signals from the vertical wiring to the horizontal wiring. The level-0 routing structure is also interconnected to the level-1 routing structure via inter-level routing switches. Signals traveling between any two logic units within a common tier 0 logic tile traverse at most one directional routing switch within the level-0 routing structure. As a result, the path delay between any two logic units is approximately equal and independent of the placement of the logic units within the tier 0 logic tile. Signals traveling between any two logic units in different tier 0 logic tiles traverse at most one directional routing switch within the level-1 routing structure and two inter-level routing switches. The path delay between any two logic units in different tiles is also approximately equal and independent of the placement of the logic units within the different tier 0 logic tiles. Additionally, the routing delays throughout the FPGA are independent of fanout of the routing net and independent of the number of wires used for the net.

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Albuquerque, NM, United States of America

David G Mavis