Globalfoundries Inc.

Motorola Corporation

Advanced Micro Devices Corporation

David G Farber

Anthony Mowry

Fred N Hause

Markus Lenski

Michael J Austin

John E Moore

Wei E Wu

Terry Grant Sparks

Phillip E Crabtree

Michael J Hartig

Jeffrey D Rose

Danny R Babbitt

Jason A Rivers

Ai Koh

A multi-core microprocessor provides an indication of the power management state of each of the cores on output terminals. Cooling of the cores is adjusted responsive to the indication of the power management state of the respective cores with additional cooling being provided to those cores in a more active state and less cooling provided to those cores in a less active state.

Heat management using power management information

By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.

Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside

A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.

Method of optimizing sidewall spacer size for silicide proximity with in-situ clean

Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic 'miller' capacitance.

Air gap spacer formation

A process for forming a semiconductor device includes placing a substrate (,) into an apparatus (,), creating a plasma, and processing the substrate (,). The apparatus (,) includes an electromagnetic source (,), a bulk material (,), and a first barrier layer (,). The bulk material (,) is between the electromagnetic source (,) and an interior (,) of the apparatus (,). The first barrier layer (,) is between the bulk material (,) and the interior (,). A process for operating an apparatus (,) includes forming a polymer layer along an inorganic layer (,or,), wherein the polymer layer is formed within the apparatus (,); removing the polymer layer to expose the inorganic layer (,, or,); and etching at least a portion of the exposed inorganic layer (,, or,). Typically, the inorganic layer (,, or,) is semiconductive or resistive.

Process for forming a semiconductor device and a process for operating an apparatus

A method and apparatus for characterizing processing operations is presented. Following exposure of a wafer to plasma, the surface charge distribution pattern on the wafer is measured. The surface charge distribution pattern on the wafer is then compared with known surface charge distribution patterns to determine if the measured charge distribution pattern correlates to desirable patterns associated with successful performance of one or more processing steps. In some embodiments, the comparison of the measured charge distribution pattern can be used to detect specific problems in one or more processing steps such that corrective action can be taken in a timely manner. The comparison between the measured charge distribution pattern and known charge distribution patterns may be performed using image comparison or using quantitative comparisons based on charge levels measured within each pattern.

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Austin, TX, United States of America

David G Farber