Sk Hynix Nand Product Solutions Corp.

David G Dreyer

Henry C Chu

David J Pelster

Mark Anthony Sumabat Golez

Bhargavi Govindarajan

Joey Rodgers

Mechanisms for controlling background wear leveling are provided, including: increasing a first counter; comparing the first counter to a first threshold; and in response to the first counter meeting the first threshold: decreasing the first counter by a value of the first threshold; and triggering background wear leveling. In some embodiments, the first counter is increased in response to receiving a write trigger. In some embodiments, the first threshold is based upon a page size and a number of planes of physical media of an SSD. In some embodiments, the mechanisms further comprise: incrementing a second counter in response to receiving a host write trigger; comparing the second counter to a second threshold; and in response to the second counter meeting the second threshold, decreasing the second counter by the second threshold, wherein the increasing the first counter is performed in response to the second counter meeting the second threshold.

Systems, methods, and media for controlling background wear leveling in solid-state drives

A method includes determining a write amplification factor for a particular NAND-based memory device and a host coupled to the NAND-based memory device and includes calculating a bandwidth of the host. Based on the write amplification factor and the bandwidth of the host, a resource of the NAND-based memory device is allocated between the host and a garbage collection process of the NAND-based memory device.

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Oronoco, MN, United States of America

David G Dreyer