Cypress Semiconductor Corporation

International Business Machines Corporation

David G Chapman

Richard Michael Parent

Timothy E Fiscus

Donald W Schmidt

John Atkinson Fifield

Rajaram B Krishnamurthy

Benjamin P Segal

Carl Joseph Parris

Mark David Jacunski

Steven William Tomashot

Nicholas Martin Van Heel

Erik A Nelson

David E Douse

Alan D Norris

David P Monty

Angel Nunez Mencias

Jakob Christopher Lang

Volker Boenisch

Gerd Konrad Bayer

William E Corbin, Jr

William R Corbin

Lin Ma

Tim Fiscus

Anupam I Arora

Chris Smith

Christopher L Smith

A method for updating software in a computer system, comprising at least a central processor and multiple adapter cards, wherein the adapter cards are attached to a network, the method comprising (i) the central processor generating a distribution map based on configuration data of the network (); (ii) the central processor sending the software update data and the distribution map to a receiving adapter card of the adapter cards; (iii) in response to receiving the software update data and the distribution map, the receiving adapter card applying the received software update data and creating at least one modified distribution map.

Updating software in multiple adapter cards

A method includes processing an application by a host including one or more processors and distributing at least a portion of the application to an accelerator for execution. The method includes instructing the accelerator to create a buffer on the accelerator and instructing the accelerator to execute the portion of the application, wherein the accelerator writes data to the buffer. The method also includes instructing the accelerator to transmit the data in the buffer to the host before the application requests the data in the buffer. The accelerator aggregates the data in the buffer before transmitting the data to the host based upon one or more runtime conditions in the host.

Distributed function execution for hybrid systems

A system for distributed function execution, the system includes a host in operable communication with an accelerator. The system is configured to perform a method including processing an application by the host and distributing at least a portion of the application to the accelerator for execution. The method also includes instructing the accelerator to create a buffer on the accelerator, instructing the accelerator to execute the portion of the application, wherein the accelerator writes data to the buffer and instructing the accelerator to transmit the data in the buffer to the host before the application requests the data in the buffer. The accelerator aggregates the data in the buffer before transmitting the data to the host based upon one or more runtime conditions in the host.

A wordline driver circuit can include single stage level shifters to translate a low voltage level (VGND to Vcc) to a high voltage level (Vnwl to Vpp). A wordline driver can further include a two-stage discharge circuit to pull down a wordline from a boosted high voltage Vpp to a boosted low voltage Vnwl. A two-stage discharge circuit can include (i) a first discharge path that can pull the wordline toward a first low voltage VGND; and (ii) a second discharge path that can pull the wordline toward a lower boosted low voltage Vnwl. Initially discharging a wordline to a first low voltage can reduce the amount of charge injected into a boosted low voltage Vnwl supply. A two-stage discharge circuit can be self timed or externally timed.

Dual-voltage wordline drive circuit with two stage discharge

In one arrangement, a semiconductor memory device can include a sense amplifier circuit () having drive high transistors (P/P), drive low transistors (N/N) and equalization transistors (N-N). Such transistors can have a body bias (VbiasN, VbiasP) that varies according to the operation conditions of the semiconductor memory device. Such variations can include any of: manufacturing process variations, operating temperature, or operating voltage.

Sense amplifier circuit and method of operation

A semiconductor device memory device () can include a sense amplifier () enabled according to a first sense signal (setn) and a second sense signal (setp). In a sense operation, a first sense signal (setn) can be driven to a first, below ground potential. Subsequently, in the same sense operation, the first sense signal (setn) can be raised and maintained at a ground potential. Such an approach can substantially eliminate a sense amplifier stall condition that can occur under low temperature and/or low voltage operation. According to another aspect of the embodiments, a more negative logical '0' value can be written back into the memory cell during an access and/or refresh operation. This more negative value is available due to the below ground level provided during a sense operation.

Sense amplifier circuit and method

A defect current contribution elimination technique may be suitable for dynamic random access memories (DRAMs) and other memory devices. A defect current can be eliminated by using an isolation circuit () between bitlines (-and-) and an associated sense amplifier circuit (). Isolation circuit () can be controlled by programmable elements, such as fusible links, which are blown at wafer test to isolate the defective bitlines from the sense amplifier circuit. Isolated, defective bitlines may initially float, but based upon the type of defect, such bitlines can be resistively tied to another element, and as a result no DC current will flow. According to another implementation, controllable devices are placed between wordlines () and the wordline driver circuits (-). A current path through a defective wordline can be similarly cut-off.

Method and circuit for reducing defect current from array element failures in random access memories

One embodiment of the present invention provides a latch hysteresis receiver circuit having reduced crowbar current. Within the present embodiment, the latch hysteresis receiver circuit comprises an input stage and a latch hysteresis switching element coupled to the input stage. Additionally, the latch hysteresis receiver circuit comprises a pass gate coupled to the latch hysteresis switching element and to an output of the latch hysteresis receiver circuit. It is noted that the pass gate may be for restricting current that flows through the latch hysteresis switching element.

Reducing crowbar current in a latch hysteresis receiver

A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) controlling the background operations in one or more sections of the memory array in response to one or more control signals and (ii) presenting the one or more control signals and one or more decoded address signals to one or more periphery array circuits of the one or more sections.

Method and architecture for reducing the power consumption for memory devices in refresh operations

A power supply detecting input receiver circuit () can include a multiplexing capability that can select one of at least two power supplies during a non-critical timing period. Such selection of a power supply can reduce both the standby and the active current of input receiver circuit (). In one arrangement, an input receiver circuit () can include a comparator (), a latch (), and a select circuit (). A latch () can be enabled to indicate a selection of a supply upon a circuit power-up, as but one example. A method is disclosed that includes comparing at least two supply voltages, setting a latch to indicate a selected supply, and providing the selected supply to an input receiver. The receiver output signal may be voltage-translated to a suitable internal supply level.

Power supply detecting input receiver circuit and method

A method for testing the data strobe window (DQS) and data valid window (tDV) of a memory device (e.g., a DDR-type memory device) using the window strobe of a testing system.

Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices

To overcome these problems, the present invention generates two window strobes and uses the two window strobes to determine if skew between two signals meets predetermined criteria. One of the window strobes is used to test one of the signals, and the other window strobe is generated relative to the first window strobe. The second window strobe tests the other signal (or signals, if they are data signals). From the tests of the two window strobes, it can be determined if the skew between the first and second signals meets predetermined criteria. In particular, the two window strobes are placed relative to each other and to the signals being tested in such a way that when both window strobes indicate passing conditions, skew between the two signals is guaranteed.

Method for testing and guaranteeing that skew between two signals meets predetermined criteria

A method for reducing power consumption during background operations in a memory array with a plurality of sections comprising the steps of (i) enabling the background operations in one or more sections of the memory array when one or more control signals are in a first state and disabling the background operations in one or more sections of the memory array when the one or more control signals are in a second state and (ii) generating the one or more control signals in response to an address signal.

A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.

Programmable delay element and synchronous DRAM using the same

A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.

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Clinton Corners, NY, United States of America

David G Chapman