Schlumberger Technologies, Inc.

Schlumberger Systems & Services, Inc.

David G Abdoo

A formatter for combining timing signals with data from an algorithmic pattern generator (APG). In the disclosed embodiment, the formatter receives address signals from an APG and timing signals from a timing unit. Each timing signal from the timing unit corresponds to an address signal received from the APG. The address and timing signals are communicated to a signal select unit wherein each timing signal selects its corresponding APG address signal. The selected APG address signal then is communicated to a signal combining unit which combines the APG address with its corresponding timing signal and generates leading edge and trailing edge marker pulses having a user-specified pulse width.

Apparatus for combining signals from first and second information

A timing generator for generating timing signals representing the leading and trailing edges of test pulses. In one embodiment of the invention, a period circuit repetitively measures time intervals, or periods, based on signals from a clock circuit, and a marker circuit generates timing signals representing leading edge and trailing edge markers precisely within each period. The period circuit comprises a period-end memory having a plurality of storage locations which are addressed by a modulo(n) counter. To support multiple timing sets, or timing cycles, one or more of the most significant bits of the address field for the period-end memory may be reserved for designating each timing signal. The time interval measured by the period-end memory may be selectively extended by delaying the clocking signal used for incrementing the modulo(n) counter. The marker circuit comprises leading edge and trailing edge marker memories for storing values indicating where in a period a leading edge or a trailing edge marker is generated. The marker circuit further comprises extended cycle leading edge and trailing edge marker memories for storing values indicating where in a later timing cycle a marker is to be generated. Leading edge and trailing edge marker vernier memories are provided for storing values used to indicate the exact placement of markers within the time interval. Leading edge and trailing edge end-of-cycle marker memories are used for generating leading edge and trailing edge markers at the end of a particular timing cycle. Leading edge and trailing edge marker inhibit memories are used for inhibiting marker generation within a particular timing cycle.

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Simi Valley, CA, United States of America

David G Abdoo