Advanced Micro Devices Corporation

Globalfoundries Inc.

David Francis Tobias

Richard G Russell

Morrie Altmejd

Evandro Carlos Menezes

Mark Tracy Ellis

James Raymond Magro

Michael T Clark

Carl Kittredge Wakeland

Daniel P Mann

Saf M Asghar

Michael S Quimby

Gary Michael Godfrey

Lloyd W Gauthier

Francisco Leonel Duran

Patrick Evan Maupin

Wallace Paul Montgomery

Harsha Jagasia

Faheem Hayat

W Paul Montgomery

A processor receives a command via a sideband interface on the processor to read processor state information, e.g., CPUID information. The sideband interface provides the command information to a microcode engine in the processor that executes the command to retrieve the designated processor state information at an appropriate instruction boundary and retrieves the processor state information. That processor information is stored in local buffers in the sideband interface to avoid modifying processor state. After the microcode engine completes retrieval of the information and the sideband interface command is complete, execution returns to the normal flow in the processor. Thus, the processor state information may be obtained non-destructively during processor runtime.

Non-destructive sideband reading of processor state information

A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.

System and method for limiting processor performance

A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.

Method and apparatus for improving responsiveness of a power management system in a computing device

A baseboard management controller (BMC) integrated circuit hosts a BIOS ROM interface. The BMC includes a bus interface responsive to an access to an address range associated with host operations, e.g., an address range associated with BIOS. The BMC includes an interface coupled to communicate with a remote computer for receiving BIOS updates and/or a BIOS patches from the remote computer. Multiple computers may each include a BMC-hosted BIOS ROM interface and may be coupled to a remote computer for communicating BIOS information between the BMCs and the remote computer.

BMC-hosted boot ROM interface

System and method for controlling an intergrated circuit to enter a predetermined performance state by skipping all intermediate states based on the determined utilization of the intergrated circuit

A baseboard management controller (BMC) hosts a real-time clock and non-volatile RAM replacement that does not require a battery power supply. The BMC includes an I/O mapped interface responsive to I/O accesses to an address range associated with storage locations of a real-time clock circuit and storage locations holding configuration information. The BMC receives power when a processor coupled to the BMC is not powered. The I/O address range may includeand. A network interface may communicate information between a network external to the BMC and the real-time clock and/or the storage locations holding the configuration information. The network external to the BMC may communicate clock synchronization and/or configuration information to the BMC.

BMC-hosted real-time clock and non-volatile RAM replacement

An integrated circuit device provides an operational set point indicator. The operational set point indicator is utilized for obtaining a plurality of operational set points. Each of the plurality of operational set points can be a pair of an operational voltage and an operational frequency for application to the integrated circuit device. The operational set point indicator can be, for example, a Schmoo Class Register, a Device Identification Register, or actual operating condition information of the integrated circuit device. The Schmoo Class Register and the Device Identification Register are utilized to identify a performance state table in memory. The actual operating conditional information can be one or more entire Schmoo Plots for the device or a subset of such information. Operational set points are used during operation of the integrated circuit device, for example, in power management applications.

Processor operational range indicator

A task queue management technique leverages infrastructure provided by file and operating systems to manage task queues substantially without otherwise typical problems regarding management of the size of the queue and/or the state of the queue (e.g., empty or full) while maintaining, regulating and altering the queue and the order of tasks in the queue. Task producer code is configurable to cause one or more executable files corresponding to each of one or more tasks to be stored in a queue directory responsive to receiving the one or more tasks. A file system associates each executable file with a time stamp indicating when the executable file was stored. Task consumer code is configurable to execute the one or more executable files in an order indicated by the time stamps associated with the executable files and to remove each executable file after execution of each executable file.

File system based task queue management

Predictions may be made regarding heat removal requirements depending on certain operational characteristics of an information processing system which have been monitored over time. A fan may be controlled based on the observed operational characteristics and based on the predictions made regarding the heat removal requirements for the system. For example, system utilization by applications may be monitored, possibly along with system performance parameters such as power level and frequency. These and other operational characteristics may be used to predict heat generation so that a fan may be controlled to anticipate temperature changes and thereby flatten temperature curves over time. This may be done in addition to monitoring the ambient temperature of the system and reacting to temperature spikes that may have already occurred.

Forward-looking fan control using system operation information

A microcontroller has many internal peripheral devices. The peripheral devices are coupled to a scan path. A memory storage device that is external to the microcontroller is also coupled to the scan path. When commanded, data is shifted out of each device configuration register onto the scan path and stored in the external memory device. This is particularly useful for obtaining the states of each device without bringing down the application. Furthermore, configuration data stored in external memory can be loaded into the peripheral device configuration registers via the scan path. This invention also supports zero-volt suspend/resume which does not need extra software readable shadow registers which are often required in other architectures for reading back the current state of legacy registers which are read-only.

Method and apparatus for communicating configuration data for a peripheral device of a microcontroller via a scan path

Method and apparatus for saving peripheral device states of a microcontroller

A computer system that has multiple performance states periodically obtains utilization information for a plurality of tasks operating on the processor and determines processor utilization according to the utilization information for the plurality of tasks. The system compares the processor utilization to at least one threshold and selectively adjusts a current processor performance state to another performance state according to the comparison.

CPU utilization measurement techniques for use in power management

A computer system has multiple performance states. The computer system periodically determines if the software power state maintained by power management software that represents the power state of the processor or other computer system component matches the actual power state of the processor or other computer system component. If not, the actual power state and the software power state are resynchronized, for example, by reinitializing the power management software or otherwise causing the software power state to match the hardware power state.

Power state resynchronization

A system is provided that contains multiple control register and descriptor table register sets so that an execution context switch between X86 protected mode operating systems can be performed with minimal processing overhead. Upon receipt of a protected instruction determined to be a meta-protected instruction, the system calls a meta virtual machine (MVM) that performs the functions necessary to shift execution contexts.

Multiple protected mode execution environments using multiple register sets and meta-protected instructions

A computing system employs an unicode driver to access and control peripheral devices by abstracting commands and status data to a level above register sets of similar but potentially incompatible peripheral devices. A unicode may be generated by an operating system or the unicode driver. Unicodes are routed by a device configuration interface that passes the unicodes between the unicode driver and peripheral devices. The peripheral devices include command decoders for performing conversion between unicodes and device-specific instructions. The use of unicode drivers eliminates duplicate driver code and simplifies device configuration for the computing system.

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Pflugerville, TX, United States of America

David Francis Tobias