Arm Limited

David Francis McHale

Rahoul Kumar Varma

Man Cheung Joseph Yiu

Gareth Duncan

Marc Richard Wicks

Mike Livesley

Andrew Brookfield Swaine

Paul Kimelman

Philippe Jean-Pierre Raphalen

Ian Field

Nicholas Esca Smith

Christophe Justin Evrard

James Robert Hodgson

Cédric Airaud

A data processing apparatus is provided, which is operable to access data values associated with a respective address values. The data processing apparatus has: a processor; a main memory having a secure data values region; a cache; and cache interface logic having data transaction logic and security determination logic. The data transaction logic receives from the processor a data access request for accessing data in cache. The data access request has an associated address value and a security attribute. If the security attribute indicates that the request is a non-secure data-access request, the security determination logic determines, via a data region allocation table, whether the request is associated with the secure data values region of main memory and the non-secure data access request is allowed to complete if it is not associated with the secure data region.

Data processing apparatus security

A data processing apparatus and a method for caching data values in data processing apparatus comprising a level one cache and a level two cache is disclosed. Both the level one cache and the level two cache are operable to store the data values. The method comprises the steps of: a) receiving a transaction request in which a data transaction relating to a data value is requested to occur, the transaction request including cache policy attributes associated with an address of the data value; and b) determining from the cache policy attributes whether or not the data value can be stored by the level one cache and the level two cache and, if so, in which one of the level one cache and the level two cache the data value is to be stored in order to ensure that the data value is prevented from being stored in both the level one cache and the level two cache. Providing cache policy attributes with each data transaction enables a simple determination to be made of which cache should be used to store each data value, with other caches being prevented from storing that data value. Such an approach obviates the need to perform any complex operations in order to determine which cache should be used to store that data value. Hence, a data value may be prevented from being stored in both the level one cache and the level two cache at any one time which ensures that the level one cache and level two cache do not store duplicate data thereby increasing the likelihood of a cache hit within level one or level two for any data value.

Caching data

The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to initiate a transaction, with the transaction specifying a transaction address. A cache is interposed between at least one of the master devices and the bus and is operable to receive the transaction issued by that master device. The cache has a cache memory and a cache controller operable to control access to the cache memory. The cache controller comprises caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address. Control storage is provided identifying a trace address range specifying a trace region. Further, trace logic is provided which is operable to selectively generate as trace data one or more attributes associated with the transaction and to provide in association with that trace data a trace address selected from the trace address range. The caching logic is then operable to store the trace data at a location in the cache memory chosen dependent on the trace address. In this way, the cache can be used in a flexible manner to not only act as a normal cache but also to selectively store within the cache trace data.

Storage of trace data within a data processing apparatus

An interrupt controller and interrupt controlling method are provided for prioritizing interrupt requests generated by a plurality of interrupt sources. The interrupt controller comprises an interrupt source interface operable to receive interrupt requests generated by a first plurality of interrupt sources, and a daisy chain interface operable to receive a daisy chain interrupt request output by a further interrupt controller based on a second plurality of interrupt requests generated by a second plurality of interrupt sources. The daisy chain interface includes a priority input operable to receive a daisy chain priority signal indicating a priority associated with the daisy chain interrupt request. Prioritization logic is operable to receive the daisy chain priority signal and to apply predetermined prioritisation criteria to determine the highest priority interrupt request selected from the daisy chain interrupt request and the interrupt request generated by the first plurality of interrupt sources. An output interface is operable to output the highest priority interrupt request, the output interface including a priority output operable to provide an output priority signal indicating a priority associated with the highest priority interrupt request.

Interrupt controller and interrupt controlling method for prioritizing interrupt requests generated by a plurality of interrupt sources

A data processing apparatus controls cross-triggering of diagnostic processes on a plurality of processing devices. The data processing apparatus comprises a routing module having a plurality of broadcast channels, one or more of the broadcast channels being operable to indicate the occurrence of a diagnostic event on one or more of the plurality of processing devices. The data processing apparatus also comprises an mapping module associated with a corresponding processing device. The interface module programmably asserts diagnostic event signals from the associated processing device to one or more of the plurality of broadcast channels and programmably retrieves diagnostic events signals from processing devices other than the associated processing device from one or more of the plurality of broadcast channels. The retrieved diagnostic event data is used to facilitate triggering of a diagnostic process on the associated processing device in dependence upon said retrieved diagnostic event data.

Cross-triggering of processing devices

The present invention provides a controller and method for controlling interfacing to a data link, the data link enabling data items relating to a number of data elements to be transferred in corresponding data slots of the data link. The controller comprises at least one channel, each channel comprising a data buffer for storing data items, and a control register associated with the data buffer and arranged to store control data. The control data is settable to define for which data element or data elements data items are to be stored in that data buffer. Further, an interface mechanism is provided for controlling the transfer of data items between the at least one channel and the data slots of the data link in dependence upon said control data. This enables a generic controller to be developed, which is of an acceptable size and cost.

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David Francis McHale