Commissariat a L'energie Atomique

Stmicroelectronics Gmbh

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

David Fraboulet

Yves Morand

Simon Deleonibus

Vincent Bouchiat

Denis Mariolle

Jacques Gautier

Didier Tonneau

Nicolas Clement

Simon 40 Allée Des Giteaux Deleonibus

This invention relates to a process for manufacturing nanowire structures, the process comprising the following steps:

Method for making a wire nanostructure in a semiconductor film

A method produces a microstructure comprising an island of material confined between two electrodes forming barriers, the island () of material having lateral flanks running parallel to and lateral flanks running perpendicular to the barriers, wherein the lateral flanks of the island are defined by etching of at least one layer (), called the template layer, and the barriers are formed by damascening. The method includes (a) a first etching of the template layer using a first etching mask having at least one filiform part, and (b) a second etching of the template layer, subsequent to the first etching, using a second etching mask also having at least one filiform part, oriented in a direction forming a non-zero angle with a direction of orientation of the filiform part of the first mask, in the vicinity of the site of formation of the island.

Method for making an island of material confined between electrodes, and application to transistors

This invention relates to a process for a manufacturing a Coulomb blockade transistor. The process comprises the following steps in sequence: deposition on an insulating substrate of a source layer, a tunnel-insulating layer and an alternating stack of at least one conducting layer and at least one insulating layer, a first etching of the stack to form a filiform tab, coating of the filiform tab with an electrically insulating coating material, a second etching of the tab of the stack to form a pillar, the second etching preserving the coating material to define a groove on each side of the pillar, the formation of at least one isolated grid in the groove, and the formation of a drain in contact with one end of the pillar opposite the source layer, through at least one tunnel-insulating layer.

Processes for making a single election transistor with a vertical channel

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Quaix en Chartreuse, France

David Fraboulet