Nvidia Corporation

Simmonds Precision Products, Inc.

David Fontaine

Stephen Jones

Mark Hairgrove

Cameron Buschardt

Lucien Dunning

Vivek Kini

Sally Tessa Stevenson

Jason David Gaiser

Shirish C Gadre

Olivier Giroux

Wishwesh Anil Gandhi

Michael A Parker

Travis Gang

Ronny Krashinsky

Peter J Carini

Steven Arthur Gurfinkel

Jaydeep Marathe

Matthew B Burleigh

Ze Long

Benjamin D Mcbride

Christopher Fitzhugh

Piotr Jaroszynski

John Hubbard

Hemayet Hossain

Kyrylo Perelygin

Ashutosh Jain

John Clifton Woolley, Jr

Debajit Bhattacharya

Lukasz Krystian Ligowski

Stephen Anthony Bernard Jones

Sebastian Piotr Jodlowski

Maciej Marcin Piechotka

Xiaonan Tian

Raymond Hoi Man Wong

Kexin Yu

Sharan Chetlur

Deyu Fu

Parag Kulkarni

Magnus Strengert

Jitendra Pratap Singh Chauhan

Apparatuses, systems, and techniques to identify a location of one or more portions of incomplete graph code. In at least one embodiment, a location of one or more portions of incomplete graph code is identified based on, for example, CUDA or other parallel computing platform code.

Application programming interface to locate incomplete graph code

Apparatuses, systems, and techniques to facilitate execution graph control. In at least one embodiment, an application programming interface comprising one or more parameters is used to control which of one or more portions of graph code are to be performed.

Application programming interface to control execution of graph nodes

Apparatuses, systems, and techniques to perform an application programming interface (API) to cause dependency type information of one or more user-indicated graph nodes of a software graph to be indicated. In at least one embodiment, one or more dependency types from a graph are indicated.

Application programming interface using node dependencies

Techniques to modify executable graphs to perform different workloads. In at least one embodiment, an executable version of a first task graph is modified by applying a non-executable version of a second task graph to executable version of first task graph so that executable version of first task graph can perform a second workload of non-executable version of second task graph.

Techniques for modifying an executable graph to perform a workload associated with a new task graph

Various embodiments include a parallel processing computer system that provides multiple memory synchronization domains in a single parallel processor to reduce unneeded synchronization operations. During execution, one execution kernel may synchronize with one or more other execution kernels by processing outstanding memory references. The parallel processor tracks memory references for each domain to each portion of local and remote memory. During synchronization, the processor synchronizes the memory references for a specific domain while refraining from synchronizing memory references for other domains. As a result, synchronization operations between kernels complete in a reduced amount of time relative to prior approaches.

Thread synchronization across memory synchronization domains

Apparatuses, systems, and techniques to indicate contextual information to be used by available logical processors. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to indicate a first set of contextual information to be used by a first subset of available processors.

Techniques for using contextual information

The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

Unified memory systems and methods

Growing community of inventors

Mountain View, CA, United States of America

David Fontaine