Intel Corporation

David Finan

Thomas P Thomas

Camron B Rust

Manpreet Singh Khaira

The first-in/first-out (FIFO) buffer includes a first bank of individual storage elements for storing even data and a second bank of individual storage locations for storing odd data. Precharge elements are provided for precharging the even array while data is read from the odd array during one clock cycle and for precharging the odd array while data is read from the even array during a next subsequent clock cycle. Hence, only half of the array is precharged during any one clock cycle. The FIFO buffer is driven by a clock signal having a clock period equal to a minimum precharge time. A 3-input multiplexer is provided with 3 inputs connected, respectively, to an output line of the even array, an output line of the odd array, and an overall input line. In circumstances where data needs to be written to and read from the same storage element in one clock cycle, the multiplexer selects the input line thereby allowing the input data to bypass the storage array for immediate output. The FIFO buffer includes a FIFO read pointer circuit and a FIFO write pointer circuit, each configured as a matrix of individual 2-input AND gates. Each of the gates of the read pointer circuit are connected to a pair of linear feedback shift registers which operate to enable only one of the gates during any clock cycle for selecting only one of the storage locations for reading a bit from. The write pointer circuit has a similar configuration. Alternative embodiments are described wherein the FIFO buffer includes rows split into three or more sub-rows, rather than merely a pair of even and odd rows.

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Portland, OR, United States of America

David Finan