Chipworks Inc.

David F Skoll

Julia Elvidge

Terry Ludlow

Michael William Phaneuf

Pierrette M Breton

Ray Haythornthwaite

Dick James

Louise Weaver

Vlad Dobrotescu

Bryan Socransky

Pierrette Breton

A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one connected annotation object in order to point to errors in the design analysis.

Design analysis workstation for analyzing integrated circuits

A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics. The design analysis workstation provides facilities for performing operations on created annotation objects including grouping, cell definition, signal carrier creation, contact creation, signal propagation, net-list generation, etc. The advantages include annotation of image-mosaics using information derived from a plurality of concurrently displayed mosaic-views to facilitate tracing of interconnected busses and an understanding of interrelations between components.

A method of recalibrating to compensate for thermal drift between a micro-imaging system and a sample integrated circuit (IC) under investigation determines a planar drift using a cross-correlation between a reference calibration image and a recalibration image, and further determines a focus drift from a difference between a reference focus setting and a recalibration focus setting. The recalibration is performed on detection of a recalibration trigger event, such as expiry of a recalibration time interval. The recalibration time interval can be adaptively adjusted based on a magnitude of the thermal drift. Tile images captured since a last recalibration are recaptured if the thermal drift is too great for reliable image compensation. The system ensures seamless assembly of tile images into image photo-mosaics and increases image photo mosaic throughput.

Method and system for recalibration during micro-imaging to determine thermal drift

A mesh is created from selected focus points having locations on a surface of interest of a sample being micro-imaged. The mesh and associated focus settings of the focus points are used to define adjacent focus facets forming a focus surface substantially coincident with the surface of interest of the sample. In micro-imaging the sample, a micro-imaged portion of the surface of interest is segmented for the purpose of acquiring tile images. A tile image focus location is used to extract a tile image focus setting from the focus surface. A tile image focus determination process selects a focus facet coincident with the tile image focus location and interpolates a tile image focus setting from focus settings associated with the focus points defining the focus facet. If a coincident focus facet is not found, the tile image focus setting is set to the focus setting of a nearest focus point. Dependence on autofocus is thus eliminated, providing faster imaging and better focused images.

Method and apparatus for focusing a micro-imaging system onto a tilted or uneven sample to acquire images of the sample

Methods of caching tile image constituents of image-mosaics enable a substantially smooth real-time display of portions of the image-mosaic in a view during panning, resizing, or zooming of the view. The method includes using a predictive algorithm to identify tile images to be retrieved from a remote store through a local area network, and for sequencing requests for the retrieval of tile images from the remote store. A scheduler calculates time spent in retrieving and servicing each tile image retrieval request and proportionately pauses retrieval of tile images after each request is serviced in order to prevent over utilizing LAN resources. The advantages are that tile images to be displayed are cached in accordance with a priority to facilitate image display while network data transfers are distributed in time.

Predictive image caching algorithm

An apparatus for extracting design and layout information from image-mosaics of a progressive deconstruction of a semiconductor integrated circuit (IC) includes a visual display, a system pointer and a plurality of lockstep cursors. The visual display displays views of an area of interest of the respective image-mosaics. Each view displays one of the lock-step cursors when appropriate, as determined by a position of the system pointer. When the system pointer is within a view, a corresponding lock-step cursor is displayed as a master-cursor, while other views display a lock-step cursor that has a different size and shape than the master-cursor. All lock-step cursors move in unison under the control of the master-cursor. A method for extracting design and layout information from image-mosaics uses the lock-step cursors to quickly match features across image-mosaics, and to avoid transposition errors while tracing features from one image-mosaic to another.

Lock-step cursors for feature alignment

A method of imaging an integrated circuit using a focused ion beam system is presented. According to the method an integrated circuit is imaged in plan-view using a focused ion beam system. Circuit information is then extracted absent processing. In another embodiment, a method and system for imaging an entire IC automatically without removing the IC from the imaging system and requiring minimal operator intervention is presented. The method employs a focused ion beam system to image an exposed layer of an integrated circuit and then to etch a portion of the exposed layer in situ. Imaging and etching are repeated until substantially the entire integrated circuit is imaged. A processor is used to assemble the layers into a three-dimensional topography of the integrated circuit. Because of known relationships between layers, the mosaicing is facilitated and the final topography is more reliable than those produced by currently known computer implemented methods.

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Ottawa, Canada

David F Skoll