International Business Machines Corporation

Globalfoundries Inc.

David F Heidel

Toshiaki Kirihata

Wei Hwang

Peilin Song

Keith Aelwyn Jenkins

Franco Stellari

Michael S Gordon

Cyril Cabral, Jr

Kerry Bernstein

Kenneth Parker Rodbell

Franco Motika

Dirk Pfeiffer

Conal Eugene Murray

Robert L Wisnieff

K Paul Muller

James A Culp

Ethan Harrison Cannon

Scott Barnett Swaney

Jeffrey Alan Kash

Anthony D Polson

Daniel Ray Knebel

Richard James Evans

Jerry Don Ackaret

James Chen-Hsiang Tsang

Naoko Pia Sanda

Richard B Bhend

Alicia Wang

Jane Jones, Legal Representative

Henry Hong Ki Tang

Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of 'in-line' connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art 'side-by-side' transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in &#x201c;hardening&#x201d; of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.

In-line stacking of transistors for soft error rate hardening

An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.

Detecting chip alterations with light emission

A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.

Method and structure to reduce soft error rate susceptibility in semiconductor structures

An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, the circuit including a latch for latching and comparing the arrival time of the signal of interest to the reference clock, a clock counter in signal communication with the latch for counting the number of reference clock cycles received and latched, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, middle stages, and a last stage, and a voltage controller in signal communication with at least one of the middle stages of the delay chain for controlling the delay of the arrival time of the reference clock, wherein the voltage controller controls the first and last stages of the delay chain to retain a full voltage swing independent of the delay.

On-chip jitter measurement circuit

This embodiment replaces the use of LBIST to get a pass or no-pass result. A selective signature feature is used to collect the top failing paths, by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip, for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths, and this is compared with the stored old paths. If the order of the top paths changes, it indicates that (for example) there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.

Measuring and predicting VLSI chip reliability and failure

An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay.

A method and system are provided for accelerated detection of soft error rates (SER) in integrated circuits (IC's) due to transient particle emission. An integrated circuit is packaged for accelerated transient particle emission by doping the underfill thereof with a transient-particle-emitting material having a predetermined emission rate. The emission rate is substantially constant over a predetermined period of time for testing. Accelerated transient-particle-emission testing is performed on the integrated circuit. Single-event upsets due to soft errors are detected, and a quantitative measurement of SER is determined.

System and method for accelerated detection of transient particle induced soft error rates in integrated circuits

A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

Method of self programmed built in self test

Methods for the ready identification of dynamic defects using switching induced light emission from CMOS gates in complex integrated circuits such as microprocessors are described. The rapid increase in the complexity of logic circuits means that practical gate level identification of the sources of dynamic errors will require methods other than the gate by gate tracing of every possible path taken by a given set of instructions. The methods described here are based on the ability of picosecond imaging circuit analysis to detect the switching activity of every gate of a complex circuit in a single, passive measurement, and the ability of data processing today to compare large two- and three-dimensional files.

Image processing methods for the optical detection of dynamic errors in integrated circuits

A memory (e.g. , Dynamic Random Access Memory (DRAM)) with self-programmable Built In Self Test (BIST). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

Self programmed built in self test

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Mahopac, NY, United States of America

David F Heidel