International Business Machines Corporation

David F Craddock

Thomas Anthony Gregg

Eric N Lais

Beth A Glendening

Harry M Yudenfriend

Donald W Schmidt

Dan F Greiner

Mark S Farrell

Peter Grimm Sutton

Bruce Marshall Walk

Ronald Edward Fuhs

Bruce Leroy Beukema

Dale Francis Riedy, Jr

Gustav E Sittmann, Iii

Renato John Recio

Matthias Klein

Matthew J Kalos

Steven Lyn Rogers

Damian Leo Osisek

Richard Loise Arndt

Charles W Gainey, Jr

Richard Louis Arndt

Gregory Francis Pfister

Richard K Errickson

Peter Kenneth Szwed

Janet R Easton

Ugochukwu Charles Njoku

Frank William Brice

Thomas Schlipf

Marco Kraemer

Calvin Charles Paynton

Christoph Raisch

Ian David Judd

Anthony F Coneski

Jonathan D Bradbury

John R Flanagan

Angel Nunez Mencias

Gerhard Banzhaf

Sascha Junghans

Carsten Otte

Juan J Ruiz

Scott A Brewer

Eric A Weinmann

Gerd Konrad Bayer

Michael Jung

Elke G Nass

James M Jenks

Justin D Miller

Eric Norman Lais

Michael T Benhase

Giles R Frazier

Daniel Francis Casper

Danny Marvin Neal

David Arlen Elko

Pak-kin Mak

Alan Frederic Benner

Mark Anthony Check

Richard P Tarcza

Jeffrey M Turner

Robert J Dugan

Allan Samuel Meritt

Gary E Strait

Tan Lu

Brenton F Belmar

Carol B Hernandez

Kevin J Reilly

William Garrett Verdoorn, Jr

Andreas Kohler

Ugochukwu Njoku-Charles

Oliver G Schlag

Steven G Wilkins

Charles Gainey

Stephen Glenn Wilkins

Gustav Sittmann Iii

Brenton Francois Belmar

Charles Gainey Jr

Anthony Coneski

Mark Farrel

Gustav Iii Sittmann

Donald William Schmidt

Gustav Sittmann

A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space that maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and generates, based on the determination, a first translation of the address being accessed to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address resulting from the translation is assigned to a device accessible via the identified bus. The method generates an entry in a translation lookaside buffer. A request directed to the device is sent via the identified bus to the bus address resulting from the translation.

MMIO addressing using a translation lookaside buffer

A method for processing an instruction by a processor operationally connected to one or more buses comprises determining the instruction is to access an address of an address space. The address space maps a memory and comprises a range of MMIO addresses. The method determines the address being accessed is within the range of MMIO addresses and translates, based on determining that the address being accessed is within the range of MMIO addresses, the address being accessed using a translation table to a bus identifier identifying one of the buses and a bus address of a bus address space. The bus address space is assigned to the identified bus. The bus address resulting from the translation is assigned to a device accessible via the identified bus. Based on the instruction a request directed to the device is sent via the identified bus to the bus address resulting from the translation.

MMIO addressing using a translation table

Aspects include providing automatic access control and security for a synchronous input/output (I/O) link. Providing automatic access control and security includes initializing devices of a storage environment over a first link to verify that the devices are available within the storage environment; building a table of identifiers, where each of the identifiers is assigned one of the devices that have been initialized; and verifying a first device attempting to perform synchronous I/O commands across the synchronization I/O link by confirming that an identifier assigned to the first device is within the table of identifiers.

Access control and security for synchronous input/output links

Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and an identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.

Synchronous input/output command

Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.

A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system is configured to purge a device table cache (DTC) in response to the processor executing the program instructions. An operating system runs on the synchronous I/O computing system and issues a synchronous I/O command indicating a request to perform a device table entry transaction that has a total data length to be transferred. A device table entry is selected from a device table, loaded into the DTC, and data packets corresponding to the device table entry transaction are transferred using the selected device table entry. A host bridge processor monitors the data packets transferred using the selected table entry, and automatically purges the selected device table entry from the DTC in response to determining the transferred data packets match the total data length.

Synchronous input/output computer system including hardware invalidation of synchronous input/output context

A synchronous input/output (I/O) computing system includes a processor and a memory unit that stores program instructions. The system purges one or more address translation entries in response to the processor executing the program instructions to issue, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction. The program instructions further command the operating system to select a device table entry from a device table, load the entry into the DTC, request required address translation entries, install the required address translation entries in the address translation cache, and transfer data packets corresponding to the transaction. The program instructions further command the operating system to automatically purge the address translation cache entries associated with a transaction in response to detect that the transaction is completed.

Transmission of a message based on a determined cognitive context

A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor executing an operating system and a recipient control unit is described. The method may include issuing, by a processor, a Synchronous I/O command to the recipient control unit; receiving, with the processor, a DMA read request from the recipient control unit; converting, with the processor, the DMA read response to write a data record into memory of the recipient control unit; issuing the DMA read request to the recipient control unit, wherein the DMA read request comprises an echo read portion comprising at least one byte of information at the end of the data record written; receiving, by the processor, a DMA write confirmation comprising the echo read portion of the record; and writing the echo read portion to a status area.

Synchronous input / output hardware acknowledgement of write completions

Embodiments include a technique for management of data transactions, where the technique includes receiving, at a link interface, a packet from an I/O device, wherein the packet includes address information, and performing, by a host bridge, an address translation for the address information included in the packet. The technique also includes responsive to performing the address translation, determining a target page associated with a translated address of the packet is for at least one of a payload target page or a signaling target page, and appending a flag to a command based at least in part on the target page being associated with the translated address of the packet. The technique includes transmitting the command to an ordering controller for ordering the packet.

Management of data transaction from I/O devices

Embodiments relate to enhancing a refresh PCI translation (RPCIT) instruction to refresh a translation lookaside buffer (TLB). A computer processor determines a request to purge a translation for a single frame of the TLB in response to executing an enhanced RPCIT instruction. The enhanced RPCIT instruction is configured to selectively perform one of a single-frame TLB refresh operation or a range-bounded TLB refresh operation. The computer processor determines an absolute storage frame based on a translation of a PCI virtual address in response to the request to purge a translation for a single frame of the TLB. The computer processor further performs the single-frame TLB refresh operation to purge the translation for the single frame.

Selective purging of PCI I/O address translation buffer

Embodiments include methods, systems, and computer program products for performing synchronous data I/O. Aspects include a processor of computer system sending a store block to request data from a device through a PCIe connection, requested data having a predetermined number of data blocks, and the processor executing a data transaction loop to retrieve requested data. Executing the data transaction loop may include writing to a table prefetch trigger register on host bridge to queue up speculative prefetches in ETU for each data block. The host bridge may perform a first speculative prefetch to install a device table entry in a device table cache. The processor may further perform a second speculative prefetch to install an address translation in an address translation cache. The host bridge processes the data block received through direct memory access over the PCIe connection using the prefetched device table entry and address translation.

Synchronous data input/output system using prefetched device table entry

A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.

Synchronous input/output (I/O) cache line padding

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David F Craddock