Idaho Research Foundation, Inc.

University of Wyoming

Other

Cirrus Logic Inc.

Apex Microtechnology Corporation

David F Cox

Erik J Mentze

Herbert L Hess

Kevin M Buck

Michael J Wilcox

Donald Claude Thelen, Jr

Steven F Barrett

Anindya Bhattacharya

Anindya Bhatacharya

An apparatus and method for providing image primitives, such as edge polarity, edge magnitude, edge orientation, and edge displacement, and derivatives thereof, for an object are described. The data are obtained substantially simultaneously and processed in parallel such that multiple objects can be distinguished from one another in real time.

Cooperative optical-imaging sensor array

The system contains a first MOS transistor having a first source element, a first drain element, and a first gate element. A first low voltage current source has two ends. The ends of the low voltage current source are connected to at least two of the first MOS transistor elements. At least one first Zener clamp is in parallel with the low voltage current source.

Trimming technique for high voltage amplifiers using floating low voltage structures

A differential amplifier stage includes one active load circuit connected to a pair of cross-coupled transistors that produce a differential signal. The active load circuit controls the rise time of the differential signal. The differential amplifier stage also includes another active load circuit connected to the pair of cross-coupled transistors. The second active load circuit controls the fall time of the differential signal.

Differential amplifier stage

A shifter circuit comprises a high and low voltage buffer stages and an output buffer stage. The high voltage buffer stage comprises multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack. The transistor stack is connected between a voltage level being shifted to and an input voltage. An inverter of this stage comprises multiple inputs and an output. Inverter inputs are connected to a respective intermediate node of the transistor stack. The low voltage buffer stage has an input connected to the input voltage and an output, and is operably connected to the high voltage buffer stage. The low voltage buffer stage is connected between a voltage level being shifted away from and a lower voltage. The output buffer stage is driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.

Low voltage to high voltage level shifter and related methods

A shifter circuit comprises, in one embodiment, an input voltage divider stage comprising multiple transistors arranged in a transistor stack defining a plurality of intermediate nodes. The transistor stack is connected between an input signal and ground and has at least one output. An inverting buffer stage is connected to a supply voltage and coupled to the input voltage divider's output. The inverting buffer stage is configured to provide an inverted output signal. Means are provided for stepping up the inverted output signal, receiving a stepped up output signal and providing a level-shifted output signal at a voltage level lower than that of the input signal.

High voltage to low voltage level shifter

Shifter circuits comprise a matched translation stack comprising at least first and second stacks each of which comprising multiple transistors. The matched translation stack is configured to provide a primary logic level shift between a voltage level away from which a shift is desired (V) and a voltage level to which the shift is desired (V). One or more high voltage buffer stages are provided, at least one of which being connected with and biased by the matched translation stack. At least one high voltage buffer stage comprises multiple transistors arranged in a transistor stack that is biased by the first stack of the matched translation stack, and is connected to receive an input supplied by the second stack of the matched translation stack. The high voltage buffer stage also comprises an inverter that drives an output stage which is also driven by a low voltage buffer stage.

Low voltage to extra high voltage level shifter and related methods

Data compression encoding and decoding circuitry which eliminates the need for decode circuitry that looks for the flux reversal points, or peaks, namely the peak detector and the phase-lock-loop circuitry combination. The encoding circuitry manipulates data by encoding data in a pulse position modulation (PPM) format such that ONE's (1's) in a data stream are delayed a first predetermined time period from the prior flux reversal (transition), and the ZERO's (0's) in the data stream are delayed a predetermined second time period from the previous transition. The encoder includes timing delay calibration circuitry that controls the time difference between transitions representing ONE's and ZERO's. The timing difference being controlled by a phase-lock loop (PLL)/precision crystal oscillator circuit combination that provides a reference delay for use by ASIC delay elements. The reference delay essentially calibrates a plurality of ASIC delay elements for encoding and facilitate subsequent decoding of corresponding calibrated delay measurement of the data bits in the decoder. The decoder member includes a plurality of delay elements that are controlled by a similar PLL delay control circuit combination that facilitates placing a data bit into its proper decode value. The encoding and decoding circuitry facilitates a 200 MBPS data rate system which is usable in local area network (LAN) systems and further facilitates data throughput as high as 98%.

Growing community of inventors

Tucson, AZ, United States of America

David F Cox