Micron Technology Incorporated

Micron Semiconductor, Inc.

David F Cheffings

Howard E Rhodes

Luan C Tran

D Mark Durcan

Robert B Kerr

Fernando N Gonzalez

Martin Ceredig Roberts

Fernando Gonz&aacute;lez

A solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film is comprised of the step of providing a first layer of insitu doped film in a manner to define an upper portion and a lower portion. A second layer of undoped film is provided on top of the first layer to similarly define an upper portion and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped to obtain a desired dopant density which decreases from the upper portion to the lower portion. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.

Method of controlling outdiffusion in a doped three-dimensional film

The invention is a semiconductor memory structure having an electrically conductive substrate interconnect formed to provide electrical continuity between a buried contact region and a source/drain region of a transistor without overlap of the buried contact region with the source/drain region. The electrically conductive substrate interconnect is formed during an ion bombardment of the substrate wherein the ions enter the substrate at an oblique angle and underlie at least a portion of a region utilized to control the amount of ions entering the substrate.

Apparatus having low resistance angled implant regions

Device fabricated by a method of controlling outdiffusion from a doped three-dimensional film

Method of controlling outdiffusion in doped three-dimensional film by

Method of reducing outdiffusion from a doped three-dimensional

Method of forming an electrically conductive substrate interconnect

Electrically conductive substrate interconnect continuity region and

A well in a semiconductor wafer is partially filled by a tungsten plug having an irregular surface. There is an aluminum line exterior of the well for electrically connecting the tungsten plug into an electrical circuit. A doped polysilicon fillet having an irregular surface meshing with the irregular surface of the tungsten plug fills the portion of the well between the plug and line, making a reproducible good electrical connection between the tungsten plug and the aluminum line. The poly fillet is formed by a poly deposit and planarization performed between a tungsten plug overetch and aluminum line deposition.

Method for making a fillet for integrated circuit metal plug

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Boise, ID, United States of America

David F Cheffings