Signetics

Scientific Microsystems, Inc.

David F Allison

David A Maxwell

Albert P Youmans

An ISL structure is fabricated by a process in which impurities are introduced into a semiconductor substrate (10) of first type conductivity (P) to form major and minor portions (18 and 18a) of a first region of opposite second type conductivity (N). The minor portion has a lower net impurity concentration than the major portion and extends to a considerably lesser depth. An impurity is introduced into the major and minor portions to form a second region (24) of first type conductivity. An impurity is introduced into the second region to form a third region (30) of second type conductivity spaced laterally apart from the minor portion. Metallization is then performed to create at least one Schottky rectifying contact (32) with the major portion and ohmic contacts (38, 36, and 34) with the substrate and second and third regions.

Method of making triple diffused ISL structure

1. In a method for forming a semiconductor structure utilizing a semiconductor body, forming a grid structure in the semiconductor body, forming a support structure upon the grid structure, removing only a portion of the semiconductor body to provide a semiconductor body which has a substantially uniform thickness in the vicinity of the grid structure and in which the grid structure does not intercept the exposed surface of the semiconductor body, and forming additional grid structure in the semiconductor body joining the first named grid structure so that islands of semiconductor material are formed in the semiconductor body which are isolated from each other and from the support structure. 23. In a method for forming a semiconductor structure utilizing a semiconductor body having a surface, forming a layer of insulating material on the surface of the semiconductor body, forming a recessed grid in the layer of insulating material and extending into the semiconductor body, forming a layer of insulating material on the recessed grid adhering to said surface and having a depth which is insufficient to fill the recessed grid to form a grid structure in a semiconductor body prior to the formation of a semiconductor device in the semiconductor body, forming a support structure upon the grid structure, removing a portion of the semiconductor body and diffusing isolation fences into the semiconductor body which extend and make contact with the layer of insulating material to form a plurality of islands of semiconductor material isolated from each other and from the support structure.

Method for making semiconductor structure

Method for making a semiconductor structure having isolated islands of semiconductor material from a semiconductor body by forming a first layer of insulating material on a surface of the body having a first support structure upon the layer of insulating material and then forming grooves in the semiconductor body which extend to the layer of insulating material formed from the semiconductor body. A second layer of insulating material is then formed on the exposed surfaces of the islands. A second support structure is then formed on the second layer of insulating material. Thereafter, the first support structure is removed and circuit devices are fabricated in the isolated islands.

Semiconductor structure having a plurality of isolated islands in which semiconductor devices are formed and which are interconnected to form an integrated circuit. The islands are isolated from each other by a combination of dielectric isolation in the form of moats and regions of higher conductivity extending downwardly into the semiconductor body from the moats. The semiconductor body from which the semiconductor structure is formed has a surface with a &lt;100&gt; orientation. An etch resistant mask is formed on the surface. An anisotropic etch is utilized to provide a plurality of isolation moats extending downwardly from the surface and having inclined side walls oriented along a crystal plane different from the &lt;100&gt; plane and having bottom walls oriented along the &lt;100&gt; crystal plane of the semiconductor body. The side walls and the bottom walls of the moats are oxidized. The oxide on the bottom walls is then removed. Impurities are then caused to enter through the bottom walls to form regions of increased impurity concentration extending down from the bottom walls. Oxide is regrown on the bottom walls and the moats are filled. Devices forming parts of integrated circuits are formed in the islands. The devices are interconnected by leads extending over the moats.

Semiconductor structure

Semiconductor structure formed from a semiconductor body having an impurity of one conductivity type therein and having a major surface lying in a &lt;100&gt; plane. Moats are provided which extend through the major surface and have spaced side walls lying in a plane different from the &lt;100&gt; plane and at said surface define spaced islands. Layers of protective material are formed on the side walls of the moats. Regions of said impurity of one conductivity type and of greater concentration than that in the body extend downwardly into the body from the protective layers. An insulating material fills the moats and devices are formed in the islands. An insulating layer is formed on said surface and lead means is provided on the insulating layer and extends through the insulating layer to make contact to the devices and extends over the material in said moats to interconnect the devices in the spaced islands. It is desirable that the moats have a generally rectangular configuration with inner and outer perimeters and inner and outer corners. The outer corners are defined by diagonal, generally planar wall portions which lie in either the &lt;110&gt; plane or the &lt;111&gt; plane. If desired, the bottom of the moats can extend downwardly until the side walls form a Vee in cross-section.

Semiconductor structure and method

A high inverse gain semiconductor device including a one conductivity semiconductor substrate having a major surface and a buried region formed in said substrate of relatively high concentration one conductivity impurities extending to said major surface. A one conductivity semiconductor layer is formed on said major surface, said layer having a planar surface. An opposite conductivity base region is formed in said layer overlying said buried region and extends to said planar surface. The base region has an outwardly notched handle-shaped portion extending outward from said base region into said body and extending to said planar surface. A one conductivity additional region formed entirely within said opposite conductivity base region extends within said base region to form a relatively uniform base region exclusive of said handle-shaped portion having a relatively narrow base width between said additional region and said layer. The layer, base and additional region form a bilateral transistor capable of substantial forward gain when the additional region is utilized as an emitter and capable of relatively high inverse gain when said additional region is utilized as a collector.

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Los Altos, CA, United States of America

David F Allison