Agilent Technologies, Inc.

Adv Antest Corporation

Advantest (singapore) Pte Ltd

Verigy (singapore) Pte. Ltd.

David Eskeldson

Edmundo De La Puente

Richard A Nygaard, Jr

Emad Soubh

Steven D Draving

Brent Anthony Holcombe

Michael Frank Jones

Kenneth Rush

Glenn Wood

Bobby Joe Self

John C Kerley

Bernhard Roth

Darrin Paul Albers

Martin L Guth

Georg-Hermann Reuer

A circuit for calibrating a plurality of automated test equipment channels comprises a central measurement unit configured to provide a current to one of the ATE channels and/or to measure a current from one of the ATE channels. The central measurement unit comprises a central measurement port, which is coupled with the plurality of ATE channels via respective diodes circuited between the central measurement port of the central measurement unit and respective DUT ports of the ATE channels.

Circuit and method for calibrating a plurality of automated test equipment channels

Serial input devices (e.g., pin electronics modules) are coupled to an interface via data lines, clock lines, and select lines. A first subset and a second subset of the devices are each arrayed in columns, rows, and layers. Each data line is coupled to a respective row in the first subset and a respective row in the second subset; each clock line is coupled to a respective column in the first subset and a respective column in the second subset; and each layer in each subset is coupled to a respective select line. The interface can program a device by concurrently activating one of the data lines, one of the clock lines, and one of the select lines.

Programming multiple serial input devices

In accordance with one embodiment of the invention, a system is provided that comprises a first terminal for receiving an input testing signal during operation; a plurality of input/output terminals coupled with the first terminal; wherein the input/output terminals are configured to parallel output respective output testing signals during parallel output operation; wherein the input/output terminals are configured to parallel input testing response signals during parallel input operation from devices under test; and wherein each of the input/output terminals is electrically isolated during operation from the remaining plurality of input/output terminals.

Parallel test circuit with active devices

In one embodiment, apparatus for transmitting and receiving data includes a transmission line network having at least three input/output terminals; at least three transmit/receive units, respectively coupled to the at least three input/output terminals; and a control system. The control system is configured to, depending on a desired direction of data flow over the transmission line network, i) dynamically place each of the transmit/receive units in a transmit mode or a receive mode, and ii) dynamically enable and disable an active termination of each transmit/receive unit. Methods for using this and other related apparatus to transmit and receive data over a transmission line network are also disclosed.

Transmit/receive unit, and methods and apparatus for transmitting signals between transmit/receive units

In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function and is coupled between the tester I/O node and the DUT I/O node. The bypass circuit is coupled between the tester I/O node and the DUT I/O node and provides a signal bypass path between the tester I/O node and the DUT I/O node. The signal bypass path bypasses the test function provided by the remote pin electronics block. The control system is configured to enable and disable the bypass circuit. Methods for using this and other related apparatus to test one or more DUTs are also disclosed.

Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test

A structure and method operable to provide ESD protection for protected circuitry of automatic test equipment (ATE). In a disable mode, the first voltage potential and second voltage potential are substantially equivalent to the reference potential resulting in a clamping circuit providing a nominal clamping voltage to the protected circuit so that an ESD event having a voltage between the first voltage potential and the second voltage potential is shunted to the reference potential via first and second ESD rails, wherein the ESD event is received on a DUT node coupled to the one or more signal rails of the protected circuitry.

Method and structure for AC coupled insitu ESD protection

A description of signal behavior in the vicinity of a time and voltage of interest is produced by defining a region in the (time, voltage) plane that is a closed straight sided figure whose vertices are identified by threshold crossings offset for the voltage of interest and clocked by time delays offset from a clock time of interest. A first set of latches clocked by the time delays accumulates the state of signal behavior relative to the threshold voltages as it occurs, and their contents are subsequently transferred to a second set of latches at the start of a new clock cycle, allowing a new accumulation to begin and also allowing a detection logic circuit to operate on a unified and completed collection of indicators of what the just concluded description amounts to. The detection logic circuit responds to the combinations of latched indications to produce a signal corresponding to that description. The closed figure need not be a rectangle, and it may also serve as an indication that a signal went into a region that it should not have, e.g., an eye violation detector.

Bounding box signal detector

A sampling transition-detector sets two latches to different values when an input signal comparator referenced to the selected voltage transitions during a sample interval: at the beginning one latch receives one comparison value while at the end the other latch receives an opposite comparison value. A difference (XOR) in latched values indicates a transition through the selected voltage during the sample interval. An additional latch is set by a second input signal comparator whose reference voltage is offset slightly from the selected voltage, It also clocked at the start of the sample interval. If the two latches clocked at the start of the sample interval are different, as indicated by another XOR, then the input was between the reference voltage and its offset counterpart. The OR of the two XORs is the desired indication.

Eye diagram analyzer correctly samples low dv/dt voltages

A connector-less probe is disclosed. The probe permits probing of a board or bus without the use of a mating connector. The probe has a support attached to the probing end of the probe. A spring pin and an isolation network are attached to the support. The support is arranged substantially perpendicular to a target board during probing of a test point on the target board. The spring pin engages the test point on the target board. The spring pin is arranged substantially perpendicular to the target board when the spring pin engages the test point on the target board, and the spring pin is securely attached to the support so that the spring pin is substantially parallel to the support. The isolation network is electrically coupled to the spring pin so that the spring pin is located between the isolation network and the test point during probing of the test point. The isolation network is also securely attached to the support.

Probe for testing circuits, and associated methods

A distributed capacitive/resistive electronic device. An electronic device is described which includes a dielectric substrate, a first resistive component, a second resistive component, and a connecting component. The first resistive component is affixed to a first side of the dielectric substrate. The second resistive component is affixed to a second side of the dielectric substrate, wherein the second side is oppositely located from the first side. The connecting component is affixed to the dielectric substrate, wherein the connecting component electrically connects the first resistive component to the second resistive component, wherein the connecting component is electrically connectable to other electronic circuitry, and wherein, at a location removed from the connecting component, the second resistive component is electrically connectable to other electronic circuitry.

Distributed capacitive/resistive electronic device

Delay induced apparent amplitude desensitization in a data signal channel and its accompanying worm-like distortion in an Eye Diagram Analyzer is avoided by altering the measurement to avoid the need for any substantial delay in the path of the data channel threshold comparison signals. In a first technique, only enough delay will be inserted in the data channels to produce the relative adjustments needed to compensate for skew between the data channels, as determined by a calibration operation, and it is these de-skewed, but otherwise un-delayed, data threshold comparison signals that are, in rapid succession, clocked into the latches whose difference registers a hit at a given (time, voltage) pair. The clock path delay is then varied from a minimal value to a sufficiently large value capable of spanning a desired the number of eye diagram cycles. In a second technique, the needed amounts of de-skew delay found by the calibration operation are noted, and then the actual delays in the data path are set back to zero. The clock path delay is swept as in the first technique. The de-skewing operation is then performed in post-processing that produces the eye diagram after the measurement is complete. In either technique, the short width of transitions in the data threshold comparison signals that are associated with threshold values near the extremes of data signal excursion are no longer swallowed by the finite bandwidth of a long delay line, since the delay lines in the data channel paths now either introduce only just enough delay to compensate for skew (and those amounts are very short), or, do not introduce any extra delay at all.

Eye diagram analyzer with fixed data channel delays and swept clock channel delay

A probe apparatus for use with analyzing devices, primarily oscilloscopes and logic analyzers, which uses pole-zero cancellation to provide a probe with low capacitance and wide bandwidth. Pole-zero cancellation enables the probe to have constant gain at all frequencies. In one embodiment, the coaxial cable between the probe tip and the replication amplifier is terminated in its characteristic impedance to provide constant gain at all frequencies regardless of cable length. Use of pole-zero cancellation and thick film technology enables building a probe with a small, durable tip.

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Colorado Springs, CO, United States of America

David Eskeldson