International Business Machines Corporation

David Erin Moran

Daria Rose Dooling

Ralph James Williams

Gary S Ditlow

Thomas Wood Wilkins

Kimball M Watson

Timothy J O'Gorman

Richard L Moore

Gustavo Enrique Tellez

Steven W Mittl

Stephen D Thomas

Cassondra L Crotty

Lenore Marie Mullin

A method and structure for determining a listing of host processors on a network to perform a parallel application, including determining a listing of all possible hosts on the network for performing the parallel application, determining for each of the possible hosts a current capacity and a current utilization, calculating for each of the possible hosts a difference between the current capacity and the current utilization, and selecting from the listing of all possible hosts a listing of hosts based on sorting the calculated differences.

Method and apparatus to manage multi-computer supply based on an economic model

Method and apparatus to manage multi-computer supply using a model based on an economic model of supply and cost of supply

A system and method for visualizing data. Data are provided either in the form of data values of a data array or in the form of a geometric representation. A data array may be, for example, a sparse matrix. A geometric representation, may be, for example, an integrated circuit layout coded in a geometric description language. Data provided in the form of data values are associated with geometric shapes placed on a grid. Information placed on the grid is then reported to a user. If data are provided in the form of a geometric representation, then data values are extracted from the geometric representation. A graphic representation is generated from the extracted data values. The graphic representation is exhibited to a user.

Method for visualizing data

Method and apparatus to manage multi-computer supply

A method, multi-computer media and apparatus that uses an economics model to manage the demand and the resource satisfying that demand for multi-computer memory. The present invention quantifies demand as a function of space, and computer resource as a function of time, so that a computational system can meet an application demand.

Method and apparatus to manage multi-computer demand

The present invention divides a large graphics file into smaller &ldquo;frames&rdquo; of graphics files. The division process is preferably load balanced amongst any number of processors. This allows many processors to be used in parallel to divide the large graphics file and to then process the smaller output frames. Additionally, the load balancing is performed in such a manner that only portions of the graphics file need be loaded by any one processor. This saves memory and computational requirements. Preferably, the graphics file is divided in a three-dimensional manner, such that any one processor will be assigned one three-dimensional block or volume of the graphics file. The three-dimensional partition of the graphics file will become one frame, and the one processor accesses the graphics file to copy its three-dimensional partition into the new output frame.

Partitioning and load balancing graphical shape data for parallel applications

A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv&equals;i) for each of the plurality of segments based on the electrical representation.

Method to partition the physical design of an integrated circuit for electrical simulation

A method for manufacturing an integrated circuit having improved defect-limited yield. Each conductor on the integrated circuit is represented as an electrical element of a network, having branch voltages and currents. The width of the conductor is advantageously selected to have the minimum width necessary to produce signal levels that have sufficient noise margins. An integrated circuit conductive grid is thus realized having a reduced cross sectional area along a portion of various conductor element lengths, to reduce the risk that particles produced during manufacturing will result in bridging of adjacent conductor elements.

Method to improve integrated circuit defect limited yield

A method and apparatus for storing and accessing a patterned array of data for a storage device, includes inputting the array, an upper bandwidth and a lower bandwidth, defining a band within the array based on the upper bandwidth and the lower bandwidth, areas of the array outside the band contain zero value data elements. The upper bandwidth, the lower bandwidth and data within the band are stored in the storage device, and the array is reproduced based on the upper bandwidth the lower bandwidth and the data within the band.

Method and apparatus for indexing patterned sparse arrays for

A method and system are provided for determining a guard band voltage differential for testing a microprocessor. The guard band voltage differential approximates microprocessor circuit propagation delay degradation expected to occur over the life of the microprocessor. The system and method are performed by first partitioning a microprocessor into a plurality of cones of n circuit level models. Timing simulation data and degradation data are created to represent, respectively, the timing operation for each of the circuit level model circuit paths, and the hot-electron effects on propagation delay degradation for each of the circuit level models. Propagation delay is identified using this data for each of the circuit paths for the circuit level models at times corresponding to the beginning-of-life and end-of-life of the microprocessor. Propagation delay degradation is calculated as the difference between the propagation delay at these times. A range of applied power supply voltages necessary to successfully perform a functional test of the microprocessor over a corresponding range of microprocessor cycle times is experimentally determined. Based on the calculated propagation delay degradation and on the range of applied power supply voltages, a guard band voltage differential for testing the microprocessor is determined.

Method to calculate hot-electron test voltage differential for assessing

A method of assessing the tolerance of a microprocessor to propagation time degradation caused by electromigration effects and hot electron effects is provided. Reference values for interconnection resistance (IR) degradation and drain current (DC) degradation are compute, at nominal fabrication process and microprocessor lifetime application conditions. These results may be tabulated for a plurality of output driver load capacitances. Test IR degradation and test DC degradation values are calculated by scaling the reference IR and DC degradation values, respectively, for actual test conditions. The circuit propagation time and the propagation delay degradation caused by both electromigration and hot electron effects are calculated at process and lifetime environmental conditions. A timing equation is evaluated using distinctly identified components of the propagation delay degradation caused by electromigration and hot electron effects, to assess the toleration of the microprocessor to electromigration and hot electron induced propagation delay degradation.

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South Burlington, VT, United States of America

David Erin Moran