Xilinx, Inc.

Seagate Technology Incorporated

Rosemount Inc.

Vintomie Networks B.v., LLC

Honeywell G.m.b.h.

Rosemont Inc.

Fmax Technologies, Inc.

Rockley Photonics Limited

David Erich Tetzlaff

Marwan M Hassoun

Richard Esten Bohn

Peng Li

Michael J Gaboury

Stephen D Anderson

James Little

Chang-Chi Liu

Steven P Young

Kevin Arthur Gomez

Moises Emanuel Robinson

Iain Ross Mactaggart

Iain R MacTaggart

Khaldoun Bataineh

Jon David Trantham

Bruce Douglas Buch

Brian Taylor Brunn

F Erich Goetting

Michael A Nix

Vivek Raghunathan

Puskal Prasad Pokharel

Jogesh Warrior

Theodore Henry Schnaare

Mai Ghaly

Jinghui Lu

David Arlo Nelson

Karlheinz Muth

Rene Johannes Marinus Van De Veerdonk

Scott Allen Davidson

Charles Edwin Goetzinger

Mathew Power Vea

Matthew L Bibee

James P Ross

Jerome M Meyer

Brian Scott Junk

Jerry Chuang

Daniel J Ferris, Iii

Theodore L Johnson

Vivek Raghuraman

Gabriel A Maalouf

Michael Maas

Michael A Orman

Michael Mass

A system including an optical engine. In some embodiments, the system includes an integrated circuit in a first-level package, and the system includes the optical engine, in the first-level package, and the optical engine includes an electro-optical chip.

Optical engine

A first input is processed via a first configuration of a neural network to produce a first output. The first configuration defines attributes of the neural network, such as connections between neural elements of the neural network. If the neural network requires a context switch to process a second input, a second configuration is applied to the neural network to change the attributes, and the second input is processed via the second configuration of the neural network to produce a second output.

Adaptive configuration of a neural network device

Apparatus and methods are provide for a multichannel clock and data recovery (CDR) device that shares information between channels. In an example, a multiple channel communication circuit can include a plurality of clock and data recovery (CDR) circuits, each CDR circuit of the plurality of CDR circuits associated with a channel of the multiple channel communication circuit. In certain examples, each CDR circuit can be configured to detect an incoming stream of data from the channel, to determine a setting of one or more parameters for correctly sampling the data from the incoming stream, and to share an indication of the setting of the one or more parameters to an adjacent CDR circuit of the plurality of CDR circuits.

Multichannel CDR with sharing of adaptation hints and learning

A compressed format is selected for storage of a matrix based on a computation to be performed using the matrix and architecture of a storage compute device to which the matrix is stored. Data of the matrix is stored on the storage compute device according to the compressed format. The computation is performed using the data via a computation unit that resides within the storage compute device.

Storage of a matrix on a storage compute device

A logical block address space of a storage compute device is reserved for use in executing commands from a host. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second portion of the logical block address space, the second data describing a result of the computation.

Logical block addresses used for executing host commands

An apparatus includes a heat pipe with a fluid path. A first part of the fluid path is thermally coupled to a first region of a higher temperature and a second part of the fluid path thermally is coupled to a second region of a lower temperature. A difference between the higher temperature and the lower temperature induces a flow of a magnetic fluid in the fluid path. A switchable magnetic device is magnetically coupled to the fluid path. Activation of the switchable magnetic device reduces the flow of the magnetic fluid in the fluid path, which reduces heat transfer from the first region to the second region.

Switchably activated heat transfer with magnetic fluid

Apparatus and methods are provide for frame synchronization and clock and data recovery. In an example, a method can include receiving initial data of a stream of information, sampling the stream of information a plurality of times per unit interval to provide a plurality of sample intervals, integrating transition information for each sample interval, and selecting a sampling phase to sample each symbol of the stream of data using the integrated transition information.

Apparatus and methods for burst mode clock and data recovery for high speed serial communication links

Commands associated with one or more logical block addresses are received via a host interface of a storage device. Based on a timing and sequence of the commands, an extent of a file that contains the logical block addresses is determined, the file being stored on the storage device. The logical block addresses are managed internally as a unitary data structure based on determining an association between the logical block addresses and the file.

Managing data within a storage device based on file system metadata

A data object is received at a storage compute device in response to a request from a host. A requirement of the data object is determined based on a computation to be performed on the data object. The requirement related to at least speed and capacity of media used to store the data object. A tier is selected from the storage compute device based on speed and capacity characteristics of the selected tier corresponding to the requirement of the data object. The data object is stored in the selected tier.

Storage compute device with tiered memory processing

A logical block address space of a storage compute device is reserved for use in executing commands from a host. The logical block address space is not mapped to a physical address space. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second portion of the logical block address space, the second data describing a result of the computation.

Combined echo and crosstalk cancellation is provided. Frequency domain adaptive filters are used to remove or reduce the effects of echo and crosstalk for a multi-channel and full-duplex communications system. Data from each transmit channel is buffered and converted to the frequency domain. The frequency domain data is multiplied by crosstalk coefficients to obtain a frequency domain correction signal for each channel. Adaptation of the crosstalk coefficients is based on correlations between the error signals and the data from each of the transmit channels. A single frequency domain transform engine, such as a Fast Fourier Transform engine, is employed for all calculations to save power and area.

Combined echo and crosstalk cancellation

A given reference pattern is written on bit patterned media that has an initial reference pattern already disposed thereon. A write phase and frequency is detected based on the initial reference pattern and the given reference pattern is written on the bit patterned media at the detected write phase and frequency.

Writing a reference pattern to bit patterned media

This disclosure is related to measurement of latency in data paths. A latency measurement may be accomplished by calculating a roundtrip write-to-read latency based on generating a write signal and receiving a read signal approximately simultaneously. The read signal may be based on a coupling between a write element and read element. A device setting may then be adjusted based on the calculated roundtrip write-to-read latency. Further, a read/write mechanism that is used to write user data to and read user data from a data storage medium may be used to determine the roundtrip write-to-read latency. Even further, the roundtrip write-to-read latency may be determined in real-time as the data storage device is in operation.

Measurement of latency in data paths

Apparatus and method for write delay stabilization. A write driver is adapted to output bipolar write currents to write data to a memory. A preconditioning circuit is adapted to output first and second thermal preconditioning currents through the write driver to stabilize a write delay associated with the write driver to a steady-state level prior to the writing of data to the memory.

Write delay stabilization

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Minnetonka, MN, United States of America

David Erich Tetzlaff