Silicon Graphics, Incorporated

Silicon Graphics International Corporation

David Edward McCracken

Martin M Deneroff

Yuval Koren

Givargis George Kaldani

James A Stuart Fiske

David Leo McCall

John Keen

Gregory Michael Thorson

Kenneth M Sarocky

Swami Venkataraman

Allan Christie

Leonard Mark Widra

Swaminatham Venkataraman

A multiprocessor computer system includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each node controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port is connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. The memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips.

Multiprocessor node controller circuit and method

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.

A node controller ( ) in a computer system ( ) includes a processor interface unit ( ), a memory directory interface unit ( ), and a local block unit ( ). In response to a memory location in a memory ( ) associated with the memory directory interface unit ( ) being altered, the processor interface unit ( ) generates an invalidation request for transfer to the memory directory interface unit ( ). The memory directory interface unit ( ) provides the invalidation request and identities of processors ( ) affected by the invalidation request to the local block unit ( ). The local block unit ( ) determines which ones of the identified processors ( ) are present in the computer system ( ) and generates an invalidation message for each present processor ( ) for transfer thereto. Each of the present processors ( ) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit ( ) that generated the invalidation request. The local block unit ( ) determines which ones of the identified processors ( ) are not present in the computer system ( ) and generates an acknowledgment message for each non-existent processor ( ). Each acknowledgment message is transferred to the processor interface unit ( ) which generated the invalidation request.

Method and apparatus for handling invalidation requests to processors not present in a computer system

A system and method for distributing output queue space is provided that includes an output queue ( ), a input queue ( ), an asynchronous input queue ( ), and a credit allocation module ( ). The output queue ( ) has a certain number of output spaces ( ) where each output space ( ) represents an output queue credit. The output queue ( ) releases output queue credits when releasing data from output spaces ( ) and receives data in response to a command being processed from the input queue ( ). The input queue ( ) queues commands and requests a number of output queue credits in response to receiving a command. The input queue ( ) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue ( ) queues commands and requests a number of output queue credits in response to receiving a command. The asynchronous input queue ( ) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The credit allocation module ( ) receives the released output queue credits and disburses the output queue credits in response to requests for output queue credits from the input queue ( ) and the asynchronous input queue ( ).

System and method for distributing output queue space

A method for minimizing ECC bits in variable sized data formats is provided that comprises determining the number of ECC bits needed for each of a plurality of data formats and creating a common data representation for using a single implementation of error detection and correction logic for all of the plurality of data formats. The method then chooses an ECC matrix and default values for unused data bits in the common data representation such that any ECC bits beyond the minimum required for that sized data format will have known values thereby allowing smaller data formats to go through the error detection and correction logic using the common data representation. The method then retrieves a data entry having one of the plurality of data formats and formats the data entry into the common data representation. The method then populates unused bits in the common data representation with default values that are chosen to provide known values for any ECC bits that are only needed for larger data formats thereby minimizing the number of ECC bits stored in each of the plurality of data formats. Errors are detected and corrected in the common data representation.

System and method for minimizing error correction code bits in variable sized data formats

A method for controlling memory page migration in a parallel processor computer ( ) is provided that comprises requesting access to a memory page ( ) by a requester processor ( ). The method then determines whether the requester processor ( ) is a local processor or a remote processor. The method then increments a local access counter ( ) and identifies the local access counter ( ) as an incremented counter in response to determining that the requester processor ( ) is a local processor. If the requester processor ( ) is determined to be a remote processor, the method increments a remote access counter ( ) and identifies the remote access counter ( ) as the incremented counter. The method next sets a threshold processing indicator to a positive value if the incremented counter exceeds a value threshold ( ) or if a difference between the local access counter ( ) and the remote access counter ( ) exceeds a difference threshold ( ). The method then generates a system interrupt in response to a positive threshold processing indicator.

System and method for memory page migration in a multi-processor computer

A memory protection system for shared memory in a multiprocessor computer is provided that comprises a multiprocessor computer ( ) having a plurality of processor regions and a plurality of memory pages ( ). Each processor region includes one or more processors ( ). Each processor ( ) includes a cache ( ), and each memory page ( ) includes one or more cache lines ( ) for coupling to the cache ( ) of processors ( ) within the plurality of processor regions using the memory page ( ). Each memory page ( ) includes a set of protection bits ( ) associated with each processor region in the plurality of processor regions. The set of protection bits ( ) includes an acquire protection bit ( ) for each processor region in the plurality of processor regions. The acquire protection bit ( ) determines whether the associated processor is enabled to perform acquire operations on the memory page ( ). The set of protection bits ( ) also includes a release protection bit ( ) for each processor region in the plurality of processor regions. The release protection ( ) determines whether the associated processor is enabled to perform release operations on the memory page ( ).

System and method for shared memory protection in a multiprocessor computer

A configurable synchronizer (,) for DDR-SDRAM (,) is provided that includes a strobe select module (,) operable to receive a memory select signal (,) and to pass strobe signals (,) from one or more DDR-SDRAMs (,) to a number of synchronizer circuits (,) corresponding to data signals (,) passed in parallel by each DDR-SDRAM as indicated by the memory select signal (,). A rising edge latch (,) receives a rising edge data signal (,) and latches the rising edge data signal (,) through the rising edge latch (,) on a rising edge of the strobe signal (,). A falling edge latch (,) receives a falling edge data signal (,) and latches the falling edge data signal (,) through the falling edge latch (,) on a falling edge of the strobe signal (,). A data signal selector (,) receives a data order control signal (,) and forwards the rising edge data signal (,) from the rising edge latch (,) to an intermediate output (,) on either a rising edge of a memory clock cycle (,) or a falling edge of a memory clock cycle (,) followed by forwarding the falling edge data signal (,) from the falling edge latch (,) to the intermediate output (,) on an opposite edge of the memory clock cycle (,) in response to the data order control signal (,). An output latch (,) receives the intermediate output (,) and latches the intermediate output (,) through the output latch (,) to an output signal (,) on each core clock cycle (,).

Configurable synchronizer for double data rate synchronous dynamic random access memory

A memory system that includes switches for controlling data transfer that are disposed on the motherboard. The switches are selectively coupled to a controller and to connector receptacles that are adapted to receive a memory module. The memory system also includes resistors that are disposed on the motherboard for terminating data signals. In one embodiment, memory modules are accessed in pairs. That is, the data switches are used to control the flow of data signals such that data signals only flow to one pair of memory modules at any particular time. In one embodiment, the memory system of the present invention includes eight memory modules that use DDR SDRAM memory components. When 8 Mbit, 16 Mbit, 32 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 128 megabytes (Mbytes) to 1 gigabyte (Gbyte).

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San Francisco, CA, United States of America

David Edward McCracken