National Semiconductor Corporation

Freescale Semiconductor,inc.

Nxp Usa, Inc.

Sgs-thomson Microelectronics Limited

Other

At&t Bell Laboratories

Vidacco International, LLC

David Edward Bien

Siamak Delshadpour

Thai Minh Nguyen

Mark Douglas McDonald

Ali A Iranmanesh

Dejan Mijuskovic

Michael J Grubisich

Xu Jason Ma

Paul Anthony Denny

Brandt Braswell

Xu Zhang

Victor Adrian Chiriac

Merit Y Hong

Xueyang Geng

Ranjeet Kumar Gupta

Paul J Daniels

Gerrit M Foerstner

Embodiments of linear transmitter (TX) drivers are disclosed. In an embodiment, a linear TX driver includes a first transistor connectable between an input voltage and a supply voltage, a second transistor connectable between an inverted version of the input voltage and a reference voltage, a first resistor connected between the first transistor and the second transistor, where an output voltage is outputted from a node between the first resistor and the second transistor, and a second resistor connectable between the second transistor and the reference voltage.

Low-current high-linearity linear transmitter driver

A switching device may include an input terminal, an output terminal, a primary switching transistor electrically coupled between the input terminal and the output terminal, and a cascode arrangement electrically coupled between the primary switching transistor and the input terminal. The cascode arrangement may include multiple cascode transistors, each having gate terminals coupled to nodes of a voltage divider that is coupled between a positive voltage supply and a reference voltage supply. Emitter-follower bipolar junction transistors (BJTs) may be configured to control voltages at the gate terminals of the primary switching transistor and the cascode transistors to accommodate changes in the output voltage at the output terminal.

Switch with cascode arrangement

A switching device may include an input terminal, an output terminal, a primary switching transistor coupled between the input terminal and the output terminal, logic circuitry configured to receive a control signal to selectively activate the switching device, a first cascode arrangement coupled between the logic circuitry and a first reference voltage supply, and a second cascode arrangement coupled between the input terminal and the primary switching transistor. The first cascode arrangement may include cascode transistors having gate terminals coupled to a first voltage divider coupled between the first reference voltage supply and a second reference voltage supply that is coupled to the logic circuitry. The second cascode arrangement may include a first cascode transistor coupled to a fixed voltage at the first voltage divider and second and third cascode transistors coupled to variable cascode bias voltages at a second voltage divider coupled to a variable voltage input.

Embodiments of level shifters are disclosed. In an embodiment, a level shifter includes a transistor connected between an input terminal of the level shifter and an output terminal of the level shifter, a first resistor connected between a first terminal of the transistor and one of the input terminal of the level shifter and the output terminal of the level shifter, a capacitor connected between the input terminal of the level shifter and the output terminal of the level shifter, a current source connected between the output terminal of the level shifter and a fixed voltage, and a resistor divider connected between the first resistor and the output terminal of the level shifter.

High-speed wide-band low-power level shifter for high-speed applications

Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.

Fast startup technique and circuit for a receiver

Various embodiments relate to a level shifter circuit configured to generate a voltage output, including: a first charging path circuit; a second charging path circuit; and an enable circuit configured to enable the first charging path circuit and the second charging path circuit, wherein

Fast response level shifter for clamp gate control

Disclosed are an apparatus and methods for introducing additives into a fluid flow. An additive vessel, with chambers for one or more additives, is attached to a primary flow fixture in a configuration that permits a diversion of part of the primary flow through the additive vessel then back to the outlet of the primary flow fixture. When the apparatus is engaged, a part of the primary flow is diverted to the additive vessel, combines with the additive, and then is re-introduced to the fluid stream, exiting the primary flow fixture.

Methods and apparatus for introducing additives into a fluid flow

A device () includes a sensing element () having drive nodes () and sense nodes (). Parasitic capacitance () is present between drive node () and sense node (). Likewise, parasitic capacitance () is present between drive node () and sense node (). When a drive signal () is applied between drive nodes (), a parasitic current () between drive and sense nodes () and a parasitic current () between drive and sense nodes () is created due to the parasitic capacitances (). A capacitive network () is coupled between the drive node () and the sense node () to create a correction current () through capacitive network () that cancels parasitic current (). Likewise, a capacitive network () is coupled between the drive node () and the sense node () to create a correction current () through capacitive network () that cancels parasitic current ().

Sensor device with reduced parasitic-induced error

Apparatus and methods are provided for multiplier circuits having reduced phase shift. A multiplier circuit comprises an input node for an input signal and an output node for an output signal. A first multiplier is coupled to the input node and has a first multiplier output, wherein the first multiplier multiplies the input signal by a first signal to produce a second signal at the first multiplier output. A second multiplier is coupled to the output node and is matched to the first multiplier. The second multiplier multiplies the output signal by a third signal to produce a fourth signal at a second multiplier output. An amplifier is coupled to the first multiplier output and the second multiplier output and produces the output signal at an amplifier output coupled to the output node based upon the second signal and the fourth signal.

Matched multiplier circuit having reduced phase shift for use in MEMS sensing applications

Apparatus and methods are provided for converting an analog input signal to a digital output value. A quantization circuit comprises an input node and a comparator array, wherein each comparator of the comparator array is coupled to the input node. A voltage divider arrangement is coupled to the comparator array and configured to establish a respective threshold voltage for each comparator of the comparator array. The comparator array generates a digital code based on the input signal and the respective threshold voltage for each comparator. A control node is coupled to the voltage divider arrangement, wherein the control node and the voltage divider arrangement are cooperatively configured to adjust the threshold voltage for at least one comparator of the comparator array in response to a control signal at the control node.

Digitally adjustable quantization circuit

Apparatus are provided for a stacked cascode current source. An apparatus is provided for an electrical device comprising an input node and an output node. A first transistor stack is coupled to the input node. The first transistor stack includes a first transistor and a second transistor. A drain terminal and a gate terminal of the first transistor are coupled to the input node. A drain terminal of the second transistor is coupled to a source terminal of the first transistor and a gate terminal of the second transistor is coupled to the input node. A second transistor stack coupled to the first transistor stack and the output node to create a current mirror for the first transistor stack.

Stacked cascode current source

A switching circuit includes (a) a bridge circuit () with a first output () to drive a load (); and (b) a driver circuit () comprising a pair of cascode amplifiers () receiving complementary inputs and a bias voltage, wherein the driver circuit () is electrically coupled to the bridge circuit ().

Switching circuit and a method of driving a load

A switching regulator provides energy to an inductor-capacitor combination that supply a DC voltage as an output. The presence of a current that can be significantly lower than the typical load current is detected using a pulse signal that provides a measure of the current supplied by the regulator to the inductor. A comparator compares this signal to a reference voltage that is related to the current level to be detected. This reference voltage is adjustable based on the voltage applied by the regulator and the voltage being ultimately supplied as the DC output voltage. The comparator and a capacitor perform an integration function that results in a voltage that ramps upward if the current threshold is being exceeded. When this ramping voltage passes a predetermined level, a signal is provided to indicate that the threshold has been exceeded.

Detecting overcurrents in a switching regulator using a voltage dependent reference

A linear amplifier with a variable signal gain controlled by a control signal that is externally generated and based on the magnitude of the incoming signal. A shunt impedance is connected at the input of the amplifier and a feedback impedance is connected between the output and input of the amplifier. The amplifier is an inverting amplifier, thereby making the output signal phase inverse to the input signal phase. Both impedances are variable and are controlled by the control signal. Together, the signal gain of the amplifier and the values of the shunt and feedback impedances determine the overall signal gain of the circuit.

Amplifier with controllable variable signal gain

A cascode single-ended to differential converter has particular applications for use in communication, e.g. RF circuits. The converter provides higher gain, reduced noise figure and improved output level and linearity over the prior art differential pair converter. The present converter is a transconductor, converting an input voltage to a differential current output signal, i.e., two output signals of different currents, with the difference being linear to the level of voltage. The cascode amplifier output signal is used to produce a signal equal in the amplitude but 180 degrees out of phase with the signal produced by the cascode amplifier.

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Glendale, AZ, United States of America

David Edward Bien