Newisys, Inc.

Insyde Software Corporation

David Edrich

David Brian Glasco

Rajesh Kota

Carl Zeitler

Guru Prasadh

Richard R Oehler

A scalable method of determining in a firmware environment if the rate of occurrence of a detectable specified type of system event that occurs to a system component or discrete functional unit, has met a criteria with respect to a pre-selected threshold. When the meeting of the threshold criteria is detected, a previously defined action associated with the threshold criteria for the particular event can be invoked by the firmware. Embodiments may establish a sliding time-window that includes a currently detected type of system event and extends back a set duration in the past. Any occurrences of the specified event taking place earlier than the established time-window may be discarded while occurrences of the events during the specified time-window are added together with the newly detected event and compared to a threshold value to see if the threshold criteria has been met.

Method and device to perform event thresholding in a firmware environment utilizing a scalable sliding time-window

A basic input/output system (BIOS) for use in a computer system having a plurality of processors is described. The BIOS is embodied in a computer readable medium as computer program instructions which are operable to facilitate substantially simultaneous operation of the plurality of processors. According to one embodiment, the processors are simultaneously enabled to test of different portions of the system memory.

Multi-processing in a BIOS environment

A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is associated with one of the processing nodes. Each processing node includes a processor, and a memory controller for controlling access to the associated portion of the system memory, and may contain a host bridge for facilitating communication with a plurality of I/O devices. The first point-to-point architecture is operable to facilitate first transactions between the processors and the system memory. The computer system further includes at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges. The at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.

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Austin, TX, United States of America

David Edrich