Unisys Corporation

David Edgar Castle

Laurence P Flora

Greggory D Donley

Manoj Gujral

Brian Joseph Sassone

A data processing system is comprised of: a system bus having a main memory coupled thereto; multiple high level cache memories, each of which has a first port coupled to said system bus and a second port coupled to a respective processor bus; and each processor bus being coupled through respective low level cache memories to respective digital computers. In the high level cache memories, data words are stored with respective tag bits which identify each data word as being stored in one of only four states which are shared, modified, invalid, or exclusive. In the low level cache memories, data words are stored with respective tag bits which identify each data word as being stored in only one of three states which are shared, modified or invalid.

Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states

A pulse synchronizing module includes: a) a pair of input leads which respectively receive a clock signal and digital input pulses that are asynchronous to the clock signal; b) a first counter circuit which is triggered by rising edge transitions in the input pulses, and a second counter circuit which is triggered by falling edge transitions in the input pulses; c) first and second registers which, in synchronization with the clock signal, sample respective counts in the first and second counter circuits; and d) an output circuit, coupled to the first and second registers. This output circuit generates, the rising edge of an output pulse, in synchronization with the clock signal, when the count sample in the first register differs from the number of rising edges which the output circuit previously generated; and it generates the falling edge of the output pulse, in synchronization with the clock signal, when the count sample in the second register differs from the number of falling edges previously generated. With this pulse synchronizing module, the samples in the first and second registers can contain errors if the samples are taken while the counters are triggered; and despite these errors, the number of output pulses which are generated will still equal the number of input pulses.

Pulse synchronizing module

A multi-level distributed data processing system includes: 1) a system bus having a main memory coupled thereto; 2) multiple high level cache memories, each of which has a first port coupled to the system bus and a second port coupled to a respective processor bus; and, 3) each processor bus is coupled to multiple digital computers through respective low level cache memories. Further, each low level cache memory stores data words with respective tag bits which identify each data word as being shared, modified or invalid but never exclusive; and, each high level cache memory stores data words with respective tag bits which identify each data word as being shared, modified, invalid, or exclusive. By identifying a data word in a low level cache memory as shared, even when that data word is not in any other low level cache memory, the high level cache memories are able to prevent two computers on separate processor busses from modifying that data word differently; and in addition, the high level cache memories are able to track the data words which get modified.

Method and circuitry for modifying data words in a multi-level

A cache memory includes: a plurality of tag memory blocks, each of which stores multiple compare addresses; a first bus which sends a low order address to all of the tag memory blocks; a respective output from each tag memory block on which a compare address is read in response to the low order address; a second bus which carries a high order address; and, a comparator circuit which generates a miss signal when the compare address on the output from every tag memory block miscompares with the high order address. Each tag memory block further stores respective control bits with each compare address; and each tag memory block responds to the low order address by reading the compare address and the respective control bits, in parallel, on its respective output. A digital logic circuit is coupled to the outputs from all of the tag memory blocks; and this digital logic circuit selects one of the tag memory blocks to write, when the miss signal occurs, by digitally combining the control bits that are read by the low order address from all of the tag memory blocks.

Cache memory which selects one of several blocks to update by digitally

An automatically variable memory interleaving system which provides different interleaving factors for particular groups of memory modules dependent upon the number of operable modules present in the system. In a particular preferred embodiment, the interleaving factor is determined for the module containing the address corresponding to the applied memory address, and this interleaving factor is then used to select particular bits of the applied memory address for determining the module to be enabled and the module address.

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Poway, CA, United States of America

David Edgar Castle