Qlogic Corporation

Archive Corporation

David E Woodral

Richard S Moore

Gavin J Bowlby

Edward H Patrick

Kamal Kant Jain

Muralidharan Viswanathan

Yongsheng Zhang

Van K Truong

Method and system for configuring a PCI-Express device is provided. The method includes determining if a number of lanes supported by the PCI-Express device is equal to or greater than a number X, after a receiver is detected by the PCI-Express device; and setting a transfer rate depending on the number X. The PCI-Express Device includes PCI-Express core logic that receives information from a Physical Coding Sub-layer indicating if a number of lanes supported by the PCI-Express device is equal to or greater than a number X, after a receiver is detected; and a transfer rate is set depending on the number X. The value of X depends on the PCI-Express device's throughput capability and a data transfer rate.

Method and system for dynamically adjusting data transfer rates in PCI-express devices

A system and method to test a host bus adapter's ('HBAs') ability to handle stream of invalid characters is provided. A data presenter module presents data to a HBA without being aware of a data format. A data producer module that is aware of the data format and schedules special characters so that the HBA can perform alignment operations. A bit offset change module changes a bit offset that is used by the data presenter module and causes to send random serial data to the HBA, which results in loss of alignment in the HBA and causes the HBA to decode invalid characters.

Method and system for testing host bus adapters

A method and system for a PCI Express device is provided. The elastic buffer includes, a buffer control module that determines a difference between a write and read pointer value and compares the difference to a threshold value for inserting or deleting a standard symbol, wherein the threshold value is adjusted dynamically based on a slow or fast clock speed. The standard symbol is a PCI Express SKIP symbol. The method includes, determining if a clock speed is slow, wherein a monitoring register value indicates if a clock speed is slow; selecting a threshold value based on the monitoring register value; and inserting or deleting a standard symbol based on a comparison of a difference between a write and read pointer and the threshold value. The PCI Express device may be a host bus adapter operating in a storage area network or any other network.

Elastic buffer module for PCI express devices

A method and system for detecting when a receiver in a host system is present or absent to receive information from a PCI-Express device is provided. The method includes monitoring a signal received from a serial/de-serializer for transitions; re-starting a first timer when a transition is detected; and detecting a receiver's absence if a second timer has reached a maximum value after a transition is detected and a first timer cycle is incomplete. The PCI-Express device includes a receiver detection logic that determines when a receiver is absent before sending any data to the host system. The PCI-Express device may be a host adapter.

Method and system for receiver detection in PCI-Express devices

A PCI Express device is provided. The PCI Express device includes a symbol lock module that includes a state machine for detecting a special character in a serial bit stream received from a serial/de-serializer, wherein the state machine receives a first special character and verifies alignment of the special character by comparing with a previously stored alignment value and the state machine declares a symbol lock if at least more than one special character alignment matches with a same stored alignment value. The special character is a comma sequence. After a symbol lock is declared, the state machine continues to monitor incoming bit stream data and compares each new special character alignment with the previously stored alignment value. During the monitoring if a misaligned special character is detected, then the state machine waits to receive another special character before declaring a loss of synchronization.

Method and system for synchronizing bit streams for PCI express devices

A system and apparatus for startup and speed regulation of low-inertia capstan motors under circumstances where the capstan load during startup may vary widely. A stiction handler provides dynamic control of the motor drive voltage imposed to overcome stationary friction, minimizing the power consumption on startup independently of variations in drag load or motor inertia. A stepped speed-up signal is applied to the motor instead of a conventional constant current-limited signal or sawtooth ramp signal. Motor speed regulation is imposed at each step of a stepped speed-up drive signal. This invention is particularly useful, for example, in low-power magnetic tape drives that must efficiently adapt to variations in drag between one tape cassette or cartridge and another.

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Walnut, CA, United States of America

David E Woodral