International Business Machines Corporation

David E Stucki

Allen H Preston

Steven G Glassen

Jonel George

Kenneth J Oakes

Leslie W Wyman

Moon Ju Kim

Roger E Hough

Matthew A Krygowski

Harry M Yudenfriend

Robert Edward Galbraith

John Ted Rodell

Richard Cwiakala

Moon Jung Kim

Charles Franklin Webb

Jeffrey Paul Kubala

Paul Gregory Greenstein

Beth A Glendening

Jeffrey Douglas Haggar

Eugene P Hefferon

Allan Samuel Meritt

Marten J Halma

Joseph C Elliott

Robert S Capowski

Carl Edward Clark

Martin W Sachs

Charles E Shapley

Kenneth J Fredericks

Frank W Brice

Neal T Christensen

Ronald F Hill

Assaf Marron

Suzanne M John

Frederick J Cox

Thomas O Curlee, Iii

Justin R Butwell

John C Rathjen, Jr

Paul A Malinowski

Norman Ehsan Shafa

John L Burk

Timothy J Spewak

A data processing system has a processing unit and a memory which provides a common pool of physical storage. This storage is initially assigned as either main storage or expanded storage during power on. Subsequent to the initial assignment, storage assigned as main storage or expanded storage may be unassigned and thus returned to the common pool. Once returned to the common pool, the storage may be reassigned as either main storage or expanded storage. The storage reassignment is done dynamically without requiring a reset action and transparent to the operating system and any active application programs.

Main storage and expanded storage reassignment facility

In a partitioned process environment, storage is reassigned by a shuffle of guest absolute address spaces which may be reassigned among partitions without restriction as to the position of the space to be reassigned relative to the position of the partition to which it is to be assigned. The reassignment is accomplished by adjusting the origin addresses by an adjustment value corresponding to the size of the address space of an additional memory area to be added to a selected partition. Furthermore, the size of the address space of the selected partition is increased by the same adjustment value. The system employs duplicated origin and limit arrays which are used to convert from a partition (guest) absolute address to a system (host) absolute address and uses duplicated configuration arrays by which the system absolute addresses are converted to physical memory addresses. Revised origin and limit information and configuration information is stored in an origin and limit array in the stand by state and in a configuration array in the stand by state. Autonomously operating circuitry is responsive to control signals to temporarily suspend memory commands from the input-output system, to reconfigure the origin and limit arrays and the configuration arrays to enable the system to use the revised information and, thereafter, to resume the processing of memory commands from the input-output system.

Method and apparatus for dynamic storage reconfiguration in a

Dynamic Reconfiguration of main storage and expanded storage by means of

A dynamic reconfiguration request for a change in a system's physical configuration is transmitted from a configuration controller to a hypervisor controlling operating systems executing in one or more partitions of the system. The hypervisor translates the physical reconfiguration request into a request for reconfiguration of logical resources known to the operating systems, first verifying it against an installation policy, and passes the requests to the operating systems in the partitions. The operating systems perform logical reconfiguration, then request physical reconfiguration of the hypervisor. The hypervisor initiates the physical reconfiguration through the configuration controller.

System and method for dynamically performing resource reconfiguration in

Provides a method for increasing the connectivity of I/O resources to a multiplicity of operating systems (OSs) running in different resource partitions of a computer electronic complex (CEC) to obtain sharing of the I/O resources among the OSs of the CEC, including channels, subchannels (devices), and control units (CUs). The invention provides image identifiers (IIDs) for assigning resources to the different OSs. Each shared I/O resource has a sharing set of control blocks (CBs) in which a respective CB is assigned to (and located by) a respective IID of one of the OSs. Each of the CBs in a sharing set provides a different image of the same I/O resource. The different CB images are independently set to different states by I/O operations for the different OSs, so that the OSs can independently share the same I/O resource.

Method and means for sharing I/O resources by a plurality of operating

Enables a host (hypervisor) to access any location in any guest zone in a large memory, when host and guest operands have small addresses that cannot access locations outside of their own zones. System hardware/microcode provides a particular number of windows for host use. Each CPU in the system has one or more window access registers (WARs), and one or more window registers (WRs). The host uses a load WAR instruction to designate each page frame (PF) in the host zone to be used as a host window, and each PF is associated with a respective window number. When the host receives an interception signal requiring the host to access a guest location represented by a guest zone identifier and a guest small address, the host designates one of its window numbers for an access to this guest location. Then, the host executes an activate WR instruction which invokes CPU hardware/microcode that generates a large absolute address for accessing this guest location in the large memory and stores it in a WR associated with the window number. When the host thereafter executes any instruction with an operand small address accessing the host window PF associated with that WR, and CPU hardware/microcode automatically substitutes that guest large address in the WR for the host operand small address for accessing the guest location.

Method of using small addresses to access any guest zone in a large

Provides a method for measuring the busy utilization time for I/O channel used by any of plural operating systems (OSs) in a CEC. The measured utilization time for any OS excludes the time shared channels are utilized by other OSs during a measurement period. A channel measurement facility (CMF) is provided in the I/O subsystem hardware and microcode for each of the OSs in the I/O subsystem. The CMF is logically constructed because it uses only a small portion of I/O resources already existing in a CEC by adding microcode to control these resources to perform the time measurement function. The resources for a logical CMF including the partial use of: an I/O processor to store identifiers of an assigned OS, the partial use of channel processors controlling channels selected by the assigned OS during a measurement period, the local storage of each I/O processor, and OS storage needed for communicating the measurement data from the CMF to the OS. Any CPU can control a measurement by issuing 'set channel measurement' instructions for starting and stopping a measurement performed asynchronously by the CMF to release the CPU for other independent CPU operations during a measurement period. The instruction can also be used to test the status of any CMF.

Channel measurement method and means

A data processing I/O system having a main storage for storing data including a software configuration definition and data processing instructions arranged in programs including an operating system, a storage device for storing I/O definition files including hardware configuration information, a processor controller for containing the hardware configuration information, and a hardware storage area (HSA) connected to the processor controller for storing a hardware configuration definition. A hardware configuration definition program (HCD) builds I/O definition files (IODFs), each IODF containing at least one I/O processor configuration definition. Each processor I/O configuration definition has a hardware token for identification. The hardware configuration information for an I/O processor configuration definition, along with a copy of its hardware token, is transferred to the processor controller by an I/O configuration program (IOCP), and a hardware configuration definition is established in the HSA. The copy of the hardware token may be fetched from the HSA and compared to hardware token of the configuration definition used to establish the software configuration definition in the main storage to determine that the software and hardware configuration definitions are synchronized. If the software and hardware configuration definitions are synchronized, dynamic changes may be made to the hardware configuration definition in the HSA. A program parameter is provided to store recovery information such that if a failure occurs during a dynamic change, the previous hardware I/O configuration may be recovered or subsequent changes can be made from the point of failure.

Establishing synchronization of hardware and software I/O configuration

A mechanism for changing the system I/O configuration definition in the channel subsystem of a data processing system without having to do a power on reset operation. The data processing system includes one or more central processing units, an I/O processor, a storage addressable by the central processors and the I/O processor, and a command mechanism for creating command-request blocks in the storage, each of which contains a requested command and data for the I/O Processor to add, delete or change elements of the I/O configuration definitions of the channel subsystem. Response-blocks are created in the storage for passing status information from the I/O processor to the central processing unit(s) indicating either successful execution of the requested command or that the I/O configuration definitions were unchanged by the command of the request-block, or when associated functions may have been performed in the execution of the command of the request-block by the I/O processor.

Dynamically changing a system I/O configuration definition

The embodiment provides selective supervisory disablement of fetch protection for a special storage subarea (such as for the first half of the first 4KB block) while fetch protection is enabled for an area containing the subarea by a single storage protect key. That is, the fetch protect for the subarea (normally provided in the fetch protect for the entire area) by the area's protect key is overriden by the selective subarea disablement control, so that accesses to the subarea are not fetch protected by the storage key. The override protection control is secured by its enablement via a field position in a control register only accessible to supervisory programming. Thus, while fetch protection is set on for a predefined 4KB block, the fetch protect override controls can disable the fetch protection for a portion of the block's real addresses (e.g. addresses 0-2047).

Storage fetch protect override controls

Growing community of inventors

Poughkeepsie, NY, United States of America

David E Stucki