Advanced Micro Devices Corporation

Legerity, Inc.

David E Norris

Larry David Hewitt

David N Suggs

Michael Hogan

Dale E Gulick

Paul G Schnizlein

Glen W Brown

Jeffrey M Blumenthal

Martin P Soques

Alfredo R Linz

Carlin D Cabler

Geoffrey E Brehmer

Michael E Spak

Ryan E Feemster

David J Guercio

Alan T Torok

Paul C Miranda

James Bunnell

Dele E Gulick

A digital wavetable audio synthesizer is described. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can ad LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create a chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects processing, the data can be provided with left and right offset volume components which determine how much of the effect is heard and its stereo position. The data is then stored in the left and right accumulators.

Wavetable audio synthesizer with left offset, right offset and effects volume control

A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Monolithic PC audio circuit

A digital wavetable audio synthesizer including a synthesizer volume generator. The volume generator causing a data sample to be multiplied by volume components that add right offset, left offset, and effects volume to the data. The left and right offsets provide stereo field positioning, and the effects volume is used in generating an echo effect. The data sample can be placed in one of sixteen fixed stereo pan positions, or alternatively the left and right offset values can be programmed to place the data anywhere in the stereo field. The synthesizer includes a register array programmed with right and left offset values for providing wavetable data with right and left offset volume components. The synthesizer also includes a first storage device for storing the right offset value, a second storage device for storing the left offset value, and multiplication circuitry connected to both storage devices for providing wavetable data with right and left offset volume components based on values stored in the first and second storage devices.

Wavetable audio synthesizer with multiple volume components and two modes of stereo positioning

A USB host controller provides transaction type status signals indicating USB activity type. The status signals include a bulk status bit signal indicative of bulk activity on a USB, a control status bit signal indicative of control activity on the USB, an isochronous status bit signal indicative of isochronous activity on the USB and an interrupt status bit signal indicative of an acknowledged interrupt on the USB. In addition a programmable mask register is provided for masking any or all of the status bits. The status bits may be combined and provided as a single signal indicative of USB activity.

Method and apparatus for monitoring universal serial bus activity

A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port; (ii) a register data port connected to the RAM input/output port and having a connection to a register data bus; (iii) timing circuitry for timing the register array operations; (iv) row and column select circuitry for respectively selecting rows and columns in said RAM; and (v) an input/output channel ready signal line connected to said timing circuitry. The RAM includes a plurality of edge bits each of which stores a value indicating whether processing of a row of data values stored in said RAM is active or inactive. The system microprocessor is disabled from accessing the RAM whenever the RAM is not idle or the microprocessor seeks to access a row of the RAM currently subject to access by the digital signal processor. If the microprocessor is disabled from writing data to the RAM, the data may be temporarily stored in the register data port until the microprocessor's access is enabled.

Enhanced register array accessible by both a system microprocessor and a

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects processing, the data can be provided with left and right offset volume components which determine how much of the effect is heard and its stereo position. The data is then stored in the left and right accumulators.

Digital wavetable audio synthesizer with delay-based effects processing

A system and method is provided for performing sound synthesis with delay-based special effects which may be algorithmically implemented using one or more time-delay elements The system implements the time-delay elements by using system memory to store time-delay data. The system and method described herein utilizes the benefits of a high bandwidth I/O bus while mitigating the disadvantages introduced by having to arbitrate for a shared system bus. By using system memory for storing time-delay data, a more cost effective PC audio system can be produced.

Computer system and method for implementing delay-based effects using

This invention is for a single monolithic audio processing integrated circuit which includes a synthesizer module, a CODEC module and an external serial data port in the CODEC module for bi-directional serial data communication between the CODEC module and an external serial data device, such as a digital signal processor. A serial data path between the synthesizer module and the CODEC module is also included.

Audio processing chip with external serial port

A power control and memory refresh rate management circuit is described. The power control circuit provides circuitry for selectively disabling or enabling modular logic circuit blocks within a VLSI integrated circuit under program control from an external processor, or for suspended circuit operation in general. In low-power modes external memory refresh signal generation circuits are provided with a low-frequency oscillator signal to conserve power.

Power control of circuit modules within an integrated circuit

A digital wavetable audio synthesizer with an LFO generator is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. The LFO generator assigns two triangular-wave LFOs to each of the 32 possible voices. One LFO is dedicated to vibrato (frequency modulation) effects and the other to tremolo (amplitude modulation) effects. It is possible to ramp the depth of each LFO into and out of a programmable maximum. The parameters for each LFO are stored in local memory. When creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations can be added to the read address to create chorus and flange effects.

Wavetable audio synthesizer with low frequency oscillators for tremolo

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

Monolithic PC audio circuit with enhanced digital wavetable audio

A static-type comparator, which compares the magnitude of a first binary number with a second binary number and determines if the first binary number is equal to, greater than, or less than the second binary number, is described. The comparator comprises a carry chain of comparison cells. Each comparison cell in the carry chain compares the magnitude of a different bit position of the first number with a corresponding bit position in the second number. The comparison cells input a first voltage signal, representing a binary value of a bit position of the first number, and a second voltage signal, representing a binary value of a corresponding bit position of the second number. A voltage signal from a voltage source Vcc is input into the carry chain and propagates through the chain until a comparison cell detects that there is a difference in magnitudes for a particular bit position. If a difference in magnitudes is detected, the comparison cell will output a voltage signal indicating whether the first number is greater than or less than the second number. If the numbers are equal, voltage signal Vcc propagates through the entire carry chain and is output. In the preferred embodiment, the comparator includes decode circuitry for decoding the carry chain's outputs. The comparator preferably also inputs a timing signal to time the comparator's operations.

Comparator circuit

A clock switcher circuit for providing at least one set of clock signals selected from a plurality of clock sources. A first clock signal having a first pulse length and a second clock signal having a second pulse length are circuit inputs. Another circuit input is a clock selection input. When the clock selection input indicates a new output clock signal, different from the then current output clock signal, should be output by the circuit, the circuit provides a means for switching to output the new output clock signal. In switching to output the new output clock signal, the circuit prevents the occurrence of the output clock signal ever having a pulse shorter than the normal pulse length of the then current output clock signal, whether the then current output clock signal is the first clock signal or the second clock signal.

Clock switcher circuit

An information storage apparatus for first-in-first-out storage and output of information includes a plurality of storage cells, an input circuit for inputting information to the storage cells, and a control circuit for controlling the operation of the apparatus in response to at least one clock signal. The storage cells are arranged to effect serial progression of information therethrough in a predetermined sequence to an output, all in response to the control circuit. The control circuit directs the information through the input circuit to the empty cell of the plurality of storage cells which is most proximate to the output of the apparatus. The input circuit provides the information to a set of first storage cells and provides an inverse representation of the information to a set of second storage cells, the first storage cells preferably being odd-numbered storage cells from the output and the second storage cells preferably being even-numbered storage cells from the output.

FIFO information storage apparatus including status and logic modules

A propagating first-in, first-out (FIFO) storage device is driven by a two-phase non-overlapping clock and includes a plurality of storage cells (C1, . . . C4) and a plurality of tracking bit cell circuits (T1, . . . T4). Each of the storage cells includes first pass gate transistors (G1, . . . G8), first inverters (INV1, . . . INV8), second pass gate transistors (G9, . . . G16), and second inverters (INV9, . . . INV16). The first pass gate transistors are responsive to a control signal from the tracking circuit for loading data input signals into the first inverter means. The second pass gate transistors are responsive to a first phase of the clock for shifting the data input signals into the second inverters.

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Austin, TX, United States of America

David E Norris