Digital Equipment Corporation

Intel Corporation

David E Morris

Matthew S Goldman

Jeffrey B Mendelson

Christopher S Bonni

Frank Calabresi

Kevin P Frenette

Thomas J Melanson

Thomas E Hirsh, Iii

Michael V Sammarco

A system and method that enhances overall computer system performance by implementing a secondary bus infrastructure to avoid data phase transaction latencies during primary bus information transfers. In accordance with an embodiment of the invention, the system includes a first bus, coupled to a host adapter and a plurality of media adapters, and a second bus, coupled to the host adapter and a select number of media adapters. The host adapter includes a host first bus controller, coupled to the first bus, and a host second bus controller, coupled to the second bus. Each of the media adapters contain a media first bus controller, coupled to the first bus, and a select number of media adapters contain a media second bus controller, coupled to the second bus. In this configuration, information initiated as a multiple data phase transaction is transferred between the host adapter and media adapters over the first bus and information initiated as a single data phase transaction is transferred between the host adapter and the select number of media adapters over the second bus.

System and method implementing a secondary bus to avoid read data latency

In a video server a transport stream is generated. The transport stream is to be transported over a circuit of a network signalling at a constant bit rate. During generation, timed program content is encoded as a variable bit rate stream. The variable bit rate stream is transported over a constant bit rate circuit of a network. While transporting the variable bit rate stream, an accumulated difference between the number of bits transported in the variable bit rate stream and the number of bits required for the constant bit rate circuit is measured periodically. In response to the measured difference, a secondary untimed content is supplied to the constant bit rate circuit at a rate which minimizes the accumulated difference, and where the secondary content is evenly distributed over the transport stream.

Apparatus and method for interleaving timed program data with secondary

In an interactive video-on-demand system, real-time programs are encoded as a transport stream including a plurality of transport stream packets. Some of the transport stream packets include timing signals indicating the real time of the program. The transport stream packets are formatted into transport cells for transport over an asynchronous transfer mode network from a source to a destination. The cells are transported at a transport rate which is determined by a network clock. The transport rate is chosen to deliver the transport stream faster than the real time of the program. While transporting the transport stream, it is determined if the transport stream is being transported ahead of the real time of the program. In this case, idle cells are injected into the transport stream to have the program arrive at the destination in the real time of the program.

Transport controller for timed program data

Method and apparatus for conditioning timed program independent of

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Lexington, MA, United States of America

David E Morris