Zilog, Inc.

Western Digital Corporation

David E McKinley

Steven M Pope

Marc B Goldstone

Dung T Nguyen

Kenneth D Donner

Rudolf Wiegand

Donn A Hopkins

A hot reconfigurable parallel bus bridging circuit is provided in a computer system which enables the computer system to communicate, via a peripheral port, with any one of plurality of incompatible standardized parallel bus systems. The hot reconfigurability of the bridging circuit of the present invention is accomplished using software to reconfigure or reprogram the various combinational logic gates, wait-state generators, and registers of the bridging circuit while the computer system is operating, without removing the bridging circuit from the computer system. The flexible hardware architecture of the present invention allows the computer system which houses this hardware to communicate with virtually any type of parallel bus system.

Hot reconfigurable parallel bus bridging circuit

A dynamic power management device for supplying power to a solid state memory integrated circuit includes power control circuitry for supplying a variable voltage to the memory integrated circuit and logic control circuitry responsive to data access activity for generating address and control signals for the memory integrated circuit and for controlling the power control circuitry to supply power to the memory integrated circuit sufficient to maintain memory information in the memory integrated circuit during periods of no data access activity and sufficient to exchange memory information with the memory integrated circuit during periods of data access activity. Power consumption of the memory integrated circuit is thereby curtailed.

Dynamic power management of solid state memories

Data is stored in and read from a semiconductor memory system including multiple memory integrated circuits in data units commonly exchanged with a rotating memory device. One or more data units to be stored are clustered with a multiplicity of other data units stored in the semi conductor memory to form a cluster of data units. The cluster of data units is compressed, and the compressed cluster of data units is then error correction coded. The compressed cluster of data units is then stored in the semiconductor memory with a multiplicity of contiguous data bits being stored in a single memory integrated circuit. Data compression reduces the number of memory integrated circuits required, thereby reducing both cost and power consumption. Data is stored in and read out of the memory integrated circuits serially such that only a single memory integrated circuit is active at a time, further reducing power consumption.

Power efficient RAM disk and a method of emulating a rotating memory disk

A method for controlling a rotating disk magnetic data storage device employing several reduced power modes which are automatically entered and exited under the control of the rotating disk device microcontroller. Two modes are provided which are fully responsive to host computer commands, and are thereby transparent to the host computer user, all providing significant power savings. An additional full power down mode is provided which can be initiated by a command from the host computer user, wherein the operational state parameters of the rotating disk device are stored in the host computer until the host computer powers on the device. At this time the stored state parameter are restored into the rotating disk device allowing it to resume its operational state immediately prior to the power suspension. Additionally, a reduced power startup procedure is provided where a low current start is first attempted, which will be successful in a high percentage of attempts, followed by a higher current attempt if the first attempt is unsuccessful. A portion of the drive circuitry is disabled during the startup procedure to further save energy.

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San Jose, CA, United States of America

David E McKinley