Intel Corporation

David E Freker

Zohar Bogin

Aditya Sreenivas

Anoop Mukker

Suryaprasad Kareenahalli

Tuong P Trieu

Amit S Bodas

Sridhar Ramaswamy

Kuljit Singh Bains

Andrew M Volk

Vincent Edward Von Bokern

Vincent E VonBokern

Kenneth M Crocker

Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Optimized memory addressing

A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.

Method and apparatus for flexible and programmable clock crossing control with dynamic compensation

A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the signals must propagate.

Method and apparatus for dynamic timing of memory interface signals

According to one embodiment, a method of transferring data across a semiconductor chip comprises transmitting data from a first Rambus asic cell to a second Rambus asic cell using clock pulses generated at a first clock generator and sampling the data at the second Rambus asic cell using clock pulses generated at a second clock generator.

Cross chip transfer mechanism for a memory repeater chip in a Dram memory system

A method and apparatus for reducing the latency of a cycle initiated by a bus-mastering agent to a memory array is described. The method and corresponding apparatus involves partially decoding a current memory cycle to generate intermediate signals and providing one or more &ldquo;safe&rdquo; indicator signals indicating the status of a previous memory cycle. A circuit receives the intermediate signals and the one or more safe indicator signals, and determines whether it is safe to issue a chip select to the memory array, notwithstanding the fact that the command to be issued to the memory array is not yet known. If the cycle is a page-hit, then no further commands or chip select signals are required for the balance of the memory cycle. If the cycle is a row-miss or page-miss, further chip select assertions are required and the responsibility to assert the chip select signal is transferred from the device to a finite state machine.

Pre-decode conditional command generation for reduced SDRAM cycle latency

According to one embodiment, a computer system is disclosed. The computer system includes a memory controller, a first Rambus channel coupled to the memory controller, a memory system coupled to the first Rambus channel and a second Rambus channel coupled to the memory system. The memory system is adaptable to determine the number of time domains on the first Rambus channel and the second Rambus channel. In a further embodiment, the memory system is adaptable to levelize memory devices coupled to the first and second Rambus channels.

Method and apparatus for detecting time domains on a communication channel

A method and apparatus for selective automatic precharge of dynamic random access memory banks is disclosed. By automatically precharging memory banks under certain conditions overall memory throughput can be improved because precharging is performed on a more selective basis. In one embodiment, the present invention provides support for multiple open banks of memory within a single memory sub-system. When multiple banks of memory are open simultaneously, a bank of memory that is less likely to be accessed in the future can be precharged when a new bank of memory is to be opened to service a memory request.

Selective automatic precharge of dynamic random access memory banks

An apparatus and method for dynamically placing portions of a memory in a reduced power consumption state. Requests to access a memory that includes a plurality of rows of memory components are received. One or more of the plurality of rows of memory components are placed in a reduced power consumption state based on the requests while one or more other rows of the plurality of rows are accessed.

Method and apparatus for dynamically placing portions of a memory in a

The present invention is a method and apparatus for addressing a memory array. The memory array has N rows of memory devices with different page sizes. A memory address corresponding to one of the N rows of memory devices is generated. A device bank address is selected corresponding to a device size and a device page size of the one of the N rows of memory devices.

Optimizing page size in mixed memory array using address multiplexing

An apparatus and method for correcting corrupted data. Access logic accesses a memory. Error detection logic generates an error signal for each data value output by the memory to indicate whether the data value has a correctable error. Correction logic requests the access logic to write to the memory a corrected version of each data value indicated by the error signal to have a correctable error.

Method and apparatus for automatically correcting errors detected in a

A method and apparatus for transferring control of a memory bus, providing access to a memory array, from a controller having control of the memory bus to a controller desiring control of the memory bus are described. The method requires generating an access request directed to the controller having control from the controller desiring control, which is then detected by the controller desiring control. A determination is made as to whether the memory bus is being used, by the controller having control, by sampling the row address strobe (#RAS) line. A fast bus transfer sequence is initiated if the memory bus is not in use, the fast transfer sequence transferring control of the memory bus to the controller desiring control after a first time period. Alternatively, a slow bus transfer sequence is initiated, when the memory bus use is over, if the memory bus is in use. The slow transfer sequence transfers control to the controller desiring control after a second time period, which is longer than the first time period and which includes a precharge period not included in the first time period. Thus when the fast transfer sequence is performed, unnecessary precharging of memory selection circuitry is avoided.

Growing community of inventors

Sacramento, CA, United States of America

David E Freker