International Business Machines Corporation

Tessera Intellectual Properties, Inc.

David E Eichstadt

Tien-Jen Cheng

Jonathan H Griffith

Roger Allan Quon

Sarah Huffsmith Knickerbocker

Kamalesh K Srivastava

Julie C Biggs

Lisa A Fanti

John Ulrich Knickerbocker

Mukta G Farooq

Subhash Laxman Shinde

William E Bernier

Randolph F Knarr

William Edward Sablinski

Wolfgang Sauter

Kevin Shawn Petrarca

John Michael Cotte

John Anthony Fitzsimmons

Richard Paul Volant

Lewis Sigmund Goldmann

Marie S Cole

Tasha E Lopez

David J Welsh

Emanuel Israel Cooper

Panayotis Constantinou Andricacos

Rosemary A Previti-Kelly

Henry Atkinson Nye, Iii

Donna S Zupanski-Nielsen

Stephen James Kilpatrick

Keith Kwong-Hon Wong

Erik J Roggeman

Emanual I Cooper

Roger A Quinn

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

Forming robust solder interconnect structures by reducing effects of seed layer underetching

A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Method of forming a bond pad on an I/C chip and resulting structure

Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

Compressible films surrounding solder connectors

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

Method for forming robust solder interconnect structures by reducing effects of seed layer underetching

A method of forming compliant electrical contacts includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads.

Compliant electrical contacts

A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.

Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer

I/C chip suitable for wire bonding

A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

Barrier for interconnect and method

A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield. An electroetch is preferred to remove the portion of the seed layer overlying the lower barrier layer.

Inhibition of tin oxide formation in lead free interconnect formation

An aqueous electrochemical etchant for etching metals in the presence of one or more metals not to be etched, the etchant including glycerol in the concentration range of 1.30 to 1.70 M, a sulfate compound having a sulfate ion concentration in the range of 0 to 0.5 M, and a phosphate compound having a phosphate ion concentration in the range of 0.1 to 0.5 M.

Electrochemical etch for high tin solder bumps

Growing community of inventors

Park Ridge, IL, United States of America

David E Eichstadt