International Business Machines Corporation

David E Douse

Erik L Hedberg

John Atkinson Fifield

Wayne Frederick Ellis

Mark David Jacunski

Endre P Thoma

John B DeForge

Steven Michael Eustis

David G Chapman

Scott J Hadderman

Nicholas Martin Van Heel

Kraig R White

Susan M Litten

Thomas M Maffitt

Scott C Lewis

Electrical mask identification of memory modules

A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source PET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.

Programmable delay element and synchronous DRAM using the same

A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations. Also, the relative placement of the current source FET to the switch device of the present invention allows the programmable delay element to quickly reach a linear and predictable state of operation.

An Off Chip Driver (OCD) having a high, a low and a high impedance (Hi-Z) state. The OCD includes an up-level pre-drive, a down-level pre-drive and a driver. The driver mirrors current in the up-level pre-drive and down-level pre-drive. Both pre-drive circuits have an unbalanced input-dependant delay to quickly turn off/on the on and off driver devices and, after a delay, reduce the drive on the turned on device to a steady state level. The delay may have a fixed length set by an inverter chain or may be dependent upon output voltage.

Off chip driver (OCD) with variable drive capability for noise control

A method and apparatus for operating a DRAM while varying the supply voltage provided thereto. A memory system is designed to attach to a DRAM. The DRAM is capable of maintaining data stored therein until supply voltage is varied beyond a predetermined voltage change level without the performance of a refresh operation. The system includes a power source coupled to the DRAM for providing supply voltage thereto and a refresh signal generator coupled to the DRAM for causing the DRAM to perform refresh operations wherein the charges associated with data bits stored within the DRAM memory cells are refreshed thereby maintaining the data integrity of data stored in the DRAM. The relative rates of supply voltage change and refresh signal provision are adjusted so as to ensure that refresh signals are provided to the DRAM prior to a point in time at which the change in supply voltage provided to the DRAM exceeds the predetermined voltage change level. Accordingly, it is possible to achieve reliable operation of the DRAM while the supply voltage provided thereto is varied.

Apparatus for varying the refresh rate for a DRAM in response to

A method and apparatus for operating a DRAM while varying the supply voltage provided thereto. A memory system is designed to attach to a DRAM. The DRAM is capable of maintaining data stored therein until supply voltage is varied beyond a predetermined voltage change level without the performance of a refresh operation. The system includes a power source coupled to the DRAM for providing supply voltage thereto and a refresh signal generation device coupled to the DRAM for causing the DRAM to perform refresh operations wherein the charges associated with data bits stored within the DRAM memory cells are refreshed thereby maintaining the data integrity of data stored in the DRAM. The relative rates of supply voltage change and refresh signal provision are adjusted so as to ensure that refresh signals are provided to the DRAM prior to a point in time at which the change in supply voltage provided to the DRAM exceeds the predetermined voltage change level. Accordingly, it is possible to achieve reliable operation of the DRAM while the supply voltage provided thereto is varied.

Maintaining data integrity in DRAM while varying operating voltages

A programmable self-time refresh circuit for a semiconductor memory and methods for programming the self-refresh rate for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.

Memory device with programmable self-refreshing and testing methods

A programmable self-timed refresh circuit for a semiconductor memory array and methods for programming the self-refresh rate and for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.

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Hinesburg, VT, United States of America

David E Douse