International Business Machines Corporation

David E DeBar

Francisco H De La Moneda

Indravadan J Shah

The current peak detector can be described as four separate sections. The first section is power distribution. The second is the analog section where the Idd current transient peak is first detected. There are two analog sections, one for Idd internal, and another for Idd external. The third section is the automatic multiplexer that controls which of the two analog sections will drive the digital section. The fourth and final section is the digital section where a voltage that is analogous to the peak current is converted to a DC voltage level with infinite memory. The digital section performs the logic function of replacing any prior digitized voltage peak with any higher voltage peak that may occur during the test period.

Transient current peak detector

A randomly accessible memory display is disclosed wherein a latching memory panel can be placed in direct optical contact with the triggering electroluminescent panel having a similar matrix. Once the glowing light from the trigger panel shines on the photosensitive resistive layer providing positive feedback, the corresponding region in the latching memory panel is latched. In accordance with the invention, a technique is disclosed for electrically reading the latched state in any one cell. This is done by selectively propagating a high frequency sinusoidal interrogation signal through each of the Y axis lines connected to the cells and measuring any phase alteration in each of the X axis lines connected to the cells, for each Y axis line interrogated. Since the resistance of the photosensitive resistor for a particular latching cell is altered if that cell is emitting light, the impedance of the cell is changed, thereby introducing a phase shift to the interrogation signal. The detection of the phase shift indicates whether the selected cell is latched in its light-emitting or light-extinguished state.

Randomly accessible memory display

A structure and process are disclosed for making a low-voltage breakdown p-n junction in a semiconductor substrate. The process comprises the step of etching a V-shaped groove in a semiconductor substrate of a first conductivity type, with an anistropic etchant, followed by depositing a layer of epitaxial semiconductor material of a second conductivity type in the V-shaped groove. There results a p-n junction with a small radius of curvature at the apex of the V-shaped groove having a correspondingly low breakdown voltage.

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Manassas, VA, United States of America

David E DeBar