Massachusetts Institute of Technology

Ergo Computing, Inc.

A.i. Architects, Inc.

David E Culler

Gregory M Papadopoulos

Arvind

Richard P Schneider

James T Pinkerton

A data flow processing system has a plurality of processing elements and memory units. Communication amongst processing elements and amongst processing elements and memory units is facilitated by an interconnection network. Each processing element is pipelined. The system operates upon data objects known as tokens. The tokens initiate activity within the processing element pipelines. Included within the activities initiated by the tokens is execution of instructions. Operands for instructions are matched in non-associative portions of memory known as activation frames. The activation frame memory locations have a state field that indicates whether a value is present or not in the activation frame. The state field may also indicate other information about an activation frame memory location. The state field is used to determine what action is taken at an activation frame memory location when an instruction is executed. The state field also determines the scheduling of execution of instructions. Moreover, the state field may be manipulated independent of a value held at an activation frame memory location.

Tagged token data processing system with operand matching in activation

A vector processor is closely integrated with a scalar processor. The scalar processor provides virtual-to-physical memory translation for both scalar and vector operations. In vector operations, a block move operation preformed by the scalar processor is intercepted, the write command in the operation is converted to a read, and data resulting from a vector operation is returned to the address specified by the block move write command. Writing of the data may be masked by a prior vector operation. Prefetch queues and write queues are provided between main memory and the vector processor. A microinstruction interface is supported for the vector processor.

Integrated scalar and vector processors with vector addressing by the

An electronic device comprising a state machine is coupled between the ROM and its socket. When armed by an arming sequence, the device responds to an address from a microprocessor during a reset operation to modify the output of the ROM. The modified output causes a jump to a routine in RAM rather than a jump in an initialization routine in the ROM. This enables a user to change the microprocessor's addressing mode from protected to real without a complete initialization of the system. Arming of the device and reset of microprocessor is caused by a protected mode routine, and after reset the mircroprocessor processes a real mode routine.

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David E Culler