Agere Systems Inc.

David E Clune

David Sonnier

Ambalavanar Arulambalam

Jian-Guo Chen

Hanan Z Moller

Nevin C Heintze

Jun Zhao

Qian Xu

Yun Peng

Michael James Hunter

Hakan I Pekcan

Duan Cheng Gang

A multicast group list (i.e., destination node address list) for a network device is circularly linked such that the list can be entered at any point and traversed back to the entry point. The list traversal is then terminated as the entire list has been processed. The data packet received at the network device for transmission to the multicast group can indicate the entry point, although there are other techniques for determining the entry point. The destination node address for the entry point is skipped, that is the multicast data packet is not transmitted to the entry point destination address.

Method and apparatus for maintaining multicast lists in a data network

Described embodiments provide a server for transferring data packets of streaming data sessions between devices. The server includes an accelerator that, for received data packets, i) extracts header fields of the packets, ii) determines, based on the header fields, a destination for the packets, and iii) provides the packets to the destination. For data to be transmitted, the accelerator i) groups the data into packets, ii) generates header fields for the packets, and iii) provides the packets to the network. A memory arbiter manages accesses to memory that buffers data and stores keys corresponding to the data sessions. A storage medium stores media files corresponding to the data sessions. A key manager includes i) a first memory for storing a master key of the server, ii) a second memory for storing one or more keys corresponding to the data sessions, and iii) a processor to encrypt and decrypt data.

Method and apparatus for secure key management and protection

A transport circuit is described for generating enable signals in different independent clock domains enabling data transfers across the clock domains. The transport circuit is used, for example, in an Ethernet receive interface where data is to be transferred from a receive clock domain to a system core clock domain for further processing. A serial to parallel data converter is used to convert the serial Ethernet data into parallel form. The output of the serial to parallel data converter is transferred to a holding register in the receive clock domain. The holding register connects to a transfer data register that is in the system core clock domain. The transport circuit provides enable signals with the proper timing to allow the transfer of data from the receive clock domain to the system core clock domain. The last data transfer swaps the interface supplied data with a status word in the holding register.

Methods and apparatus for controlling ethernet packet transfers between clock domains

In a method of accessing a single port memory, a plurality of read commands are received from a plurality of requestors for memory read access. A respective plurality of parameters corresponding to each of the plurality of read commands is stored in a memory read command queue. The parameters corresponding to one of the read commands are retrieved from the memory read command queue when the single port memory provides the data corresponding to that read command. One or more of the parameters from the memory read command queue are provided while providing the data from the memory.

Method and system for accessing a single port memory

A scheduler for shared network resources implementing a plurality of user selectable data scheduling schemes within a single hardware device. The schemes include strict priority, priority for one class plus smooth deficit weighted round robin for the other classes, bandwidth limited strict priority and smooth deficit weighted round robin for all user classes. The network operator selects one of the four schemes by enabling or disabling certain bits in the hardware device.

Method and apparatus for providing multiple data class differentiation with priorities using a single scheduling structure

A processing system comprises processing circuitry and memory circuitry coupled to the processing circuitry. The memory circuitry is configurable to maintain at least one queue structure representing a list of data units (e.g., pointers to packets stored in a packet memory). The queue structure is partitioned into two or more blocks (e.g., chunks) wherein at least some of the blocks of the queue structure include two or more data units. Further, at least some of the blocks of the queue structure may include a pointer to a next block of the queue structure (e.g., a next chunk pointer). Given such a queue structure, the processing circuitry is configurable to address a first block of the queue structure, and then address a next block of the queue structure by setting the next block pointer of the first block to point to the next block.

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Califon, NJ, United States of America

David E Clune