Taiwan Semiconductor Manufacturing Comp. Ltd.

Aiwan Semiconductor Manufacturing Company, Ltd.

David Ding-Chung Lu

Chung-Long Chang

Wen-Chih Chiou

Chia-Yi Chen

Chin-Hsiang Lin

Kuei Shun Chen

I-Lu Wu

Ching-Yu Chang

Shine Chung

Chien-Wei Wang

Ming-Shih Yeh

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

Conductor structure for three-dimensional semiconductor device

Three-dimensional semiconductor device

A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate.

Capacitors integrated with metal gate formation

A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lithography mechanism. The exposures can be done in either order, and additional exposures can be included. The higher-precision lithography mechanism can be immersion lithography and the lower-precision lithography mechanism can be dry lithography.

System and method for photolithography in semiconductor manufacturing

A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

Provided is a method and system for vapor deposition of a coating material onto a semiconductor substrate. In an embodiment, photoresist is deposited. An in-situ baking process may be performed with the vapor deposition. In an embodiment, a ratio of chemical components of a material to be deposited onto the substrate is changed during the deposition. Therefore, a layer having a gradient chemical component distribution may be provided. In an embodiment, a BARC layer may be provided which includes a gradient chemical component distribution providing an n,k distribution through the layer. Other materials that may be vapor deposited include pattern freezing material.

System and method of vapor deposition

An integrated circuit structure combining air-gaps and metal-oxide-metal (MOM) capacitors is provided. The integrated circuit structure includes a semiconductor substrate; a first metallization layer over the semiconductor substrate; first metal features in the first metallization layer; a second metallization layer over the first metallization layer; second metal features in the second metallization layer, wherein the first and the second metal features are non-capacitor features; a MOM capacitor having an area in at least one of the first and the second metallization layers; and an air-gap in the first metallization layer and between the first metal features.

MOM capacitors integrated with air-gaps

A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.

An integrated circuit structure includes a semiconductor chip including a top surface, a bottom surface, and a side surface; a metal seal ring adjacent the side surface; and an antenna including a seal-ring antenna. The seal-ring antenna includes at least a portion of the metal seal ring.

Growing community of inventors

Hsin-Chu, Taiwan

David Ding-Chung Lu