International Business Machines Corporation

David DeWitt

William Stanford Johnson

Kenneth Howard Christie

A method of manufacturing an insulated gate field effect transistor comprising providing a semiconductor body portion of one type conductivity, providing on a surface of said body portion an impurity masking layer having two adjacent apertures with the portion of the masking layer between said apertures and part of its thickness being of a masking material other than silicon dioxide and also capable of masking the silicon against oxidation, providing by impurity introduction through said apertures spaced surface regions of opposite type conductivity in said body portion, subjecting at least the surface portions of the body portion overlying the opposite type surface regions and adjacent the oxidation masking material to an oxidation treatment causing thereon the growth of a silicon dioxide that penetrates into the body portion except where masked by the oxidation masking material forming a silicon mesa under said oxidation masking material, applying a gate electrode insulated from and over the surface portion extending between the opposite type surface regions, and applying source and drain connections to the opposite type surface regions.

Method for forming a transistor comprising layers of silicon dioxide and

A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.

Non-volatile metal nitride oxide semiconductor device

A field effect transistor with spaced source and drain regions of a first type conductivity in a monocrystalline semiconductor body having a background impurity of a second opposite type conductivity, the improvement being a buried layer of a second type conductivity impurity having an average concentration higher than the impurity concentration of the background impurity that is located just beneath the insulating layer in the field regions of the device and at a greater depth in the gate region, the depth in the gate region being approximately equal to the thickness of the field insulating layer less the thickness of the gate insulating layer.

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Poughkeepsie, NY, United States of America

David DeWitt