Credence Systems Corporation

Credence Systems Coporation

David Dean Reynolds

Bryan J Dinteman

Daniel J Bedell

Roman A Slizynski

Roman Aureli Slizynski

A digitizer can be programmed to digitize an ANALOG signal with a complex frequency pattern determined in response to set of trigger signals. The digitizer includes an addressable packet memory storing a set of data packets and produces one of its stored data packets as output when addressed. The output data packet includes both PERIOD and MODE data fields. The digitizer also incudes an analog-to-digital converter for digitizing the ANALOG signal at the frequency controlled by the PERIOD data output of the packet memory. The MODE data output of the packet memory tells a trigger logic circuit how to choose a next packet memory address and selects one of the trigger signals to tell the trigger logic circuit when to change the packet memory address so as to alter the digitizing frequency.

Programmable digitizer with adjustable sampling rate and triggering modes

A digitizing system coherently samples an input signal of frequency F.sub.t and generates an output data sequence representing magnitudes of N successive samples. The digitizing system generates a timing signal by frequency dividing a clock signal of frequency F.sub.MCLK by an integer factor K and supplies the timing signal to a digitizer. The digitizer coherently samples the input signal N times over M cycles of input signal to produce an N-term data sequence representing one cycle of the input signal. The timing signal frequency sets the digitizer sampling rate. The digitizing system includes a computer programmed to execute an algorithm for finding an appropriate value for K so that the system substantially achieves coherent sampling of the input signal despite limitations in allowable ranges of K, M and N. The algorithm searches a Farey series to locate terms of the form P/Q from which it may derive candidate values of K (K=Q.sub.i *J), M (M=P*J) and N (N=Q.sub.i), wherein P and Q are relatively prime integers, J is an integer greater than 0 and Q.sub.i is an integer factor of Q. The algorithm locates the particular Farey series term most closely approximating the ratio F.sub.t /F.sub.MCLK for which candidate values of K, M and N fall within their allowable ranges. The digitizing system then frequency divides the master clock signal by that candidate value of K.

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Beaverton, OR, United States of America

David Dean Reynolds