Cisco Technology, Inc.

Nds Corporation

David Darmon

Aharon Grabovsky

Avi Klein

Yehuda Salmon

Ruben Attia

Yaacov Belenky

Uri Kaluzhny

Leonid Frenkel

Eyal Wasserman

Yigal Dahan

Lev Yudalevich

Yair Arzi

In one embodiment a device is described, the device including a memory operative to store an program, a storage operative to store a reference check value for at least one operation in the program, a processor operative to execute the program, including, determining a run-time check value upon execution of the at least one operation in the program, comparing the stored reference check value with the run-time check value, storing the run-time check value as a pre-branch run-time check value prior to entering a conditional branch of the program when the compared stored reference check value and the run-time check value are equal values, resetting the run-time check value of the executing program to the pre-branch run-time check value upon exiting the conditional branch of the program, wherein the reference check value, the run-time check value, and the pre-branch run-time check value are determined as a result of a single function. Related apparatus, methods and systems are also described.

Methods and systems for ensuring program code flow integrity

In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.

Timing based camouflage circuit

Obfuscating a multi-threaded computer program is carried out using an instruction pipeline in a computer processor by streaming first instructions of a first thread of a multi-threaded computer application program into the pipeline, the first instructions entering the pipeline at the fetch stage, detecting a stall signal indicative of a stall condition in the pipeline, and responsively to the stall signal injecting second instructions of a second thread of the multi-threaded computer application program into the pipeline. The injected second instructions enter the pipeline at an injection stage that is disposed downstream from the fetch stage up to and including the register stage for processing therein. The stall condition exists at one of the stages that is located upstream from the injection stage.

Obfuscated hardware multi-threading

Growing community of inventors

Jerusalem, Israel

David Darmon