Ceva D.s.p. Ltd.

David Dahan

Gil Drori

Omri Eisenbach

Erez Bar-Niv

Omir Eisenbach

Erez Bar Niv

Rafi Fried

A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.

Method and apparatus for accessing a multi ordered memory array

A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

System and method for providing mutual breakpoint capabilities in computing device

System and method for providing mutual breakpoint capabilities in a computing device

A 3-input adder/subtractor unit, having a first input for receiving a first operand A, a second input for receiving a second operand B, and a third input for receiving a third operand C. An add/subtract unit includes a control input for receiving a user-specified opcode, a first 3-to-2 compressor for receiving a respective least significant bit of said operands or its complement, and a Half Adder coupled to the first 3-to-2 compressor and responsive to an output thereof and to said opcode for outputting a least significant bit of a sum equal to A+B+C or A+B&#x2212;C or A&#x2212;B+C or A&#x2212;B&#x2212;C. A plurality of 3-to-2 compressors each in respect of remaining bits of the operands receive a respective bit of the operands or its complement, and a 2-input adder coupled to the 3-to-2 compressors receive respective carry and save outputs thereof and computing respective bits of the sum apart from the least significant bit.

3-input arithmetic logic unit

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Pardes Hanna, Israel

David Dahan